Distributed direct memory access provision within a data processing system

DISTRIBUTED DIRECT MEMORY ACCESS
PROVISION WITHIN A DATA PROCESSING
SYSTEM

BACKGROUND OF THE INVENTION [0001] 1. Field of the Invention

[0002] This invention relates to data processing systems. More particularly, this invention relates to the provision of distributed direct memory access management capabilities within a data processing system.

[0003] 2. Description of the Prior Art

[0004] It is known to provide data processing systems with a direct memory access controller which is able to autonomously manage data transfers. As an example, in a systemon-chip design including a CPU and a DMA controller, the DMA controller may perform regular high volume data transfers, such as screen refresh, whilst the CPU is left to control other data transfers. This reduces the processing burden upon the CPU.

[0005] It is also known to provide more than one DMA controller within a system. These may, for example, be provided on respective buses to provide separate DMA capabilities on those buses.

[0006] A problem associated with traditional DMA controllers is that they introduce a signal transfer bottleneck since they service the DMA requirements of several devices which must all be routed through the DMA controller. Where more than one DMA controller is provided, there is the additional complication of distributing control information between those DMA controllers such that they act in a coordinated fashion. A further disadvantage with the traditional approach is that the DMA controllers will tend to have a fixed priority level associated with the data transfers that they instruct and will utilise a single memory map. This provides a disadvantageously coarse level of control.

SUMMARY OF THE INVENTION

[0007] Viewed from one aspect the present invention provides an adaptor circuit comprising:

[0008] a peripheral port operable to connect to at least one peripheral device;

[0009] a system port operable to connect to a plurality of further devices;

[0010] a direct memory access manager operable to autonomously manage data transfers between one of said at least one peripheral devices coupled to said peripheral port and at least one of said plurality of further devices coupled to said system port; and

[0011] a bypass circuit coupled to said system port, said peripheral port and said direct memory access manager and operable in:

[0012] (i) a bypass mode to connect said system port to said peripheral port such that data transfers managed from outside said adaptor circuit pass between said system port and said peripheral port; and

[0013] (ii) in a direct memory access mode to connect said system port to said direct memory access manager and to connect said peripheral port to said direct memory access

manager such that said direct memory access manager autonomously manages data transfers between one of said at least one peripheral devices coupled to said peripheral port and at least one of said plurality of further devices coupled to said system port.

[0014] The present technique recognises that overall advantages can be achieved by providing a DMA capability dedicated to one or more peripheral devices and disposed in an adaptor in the path between those peripheral devices and one or more further devices. The DMA capabilities provided can be tailored to the peripheral devices to which they relate and since more DMA functionality can be provided a bottleneck in data transfer capability is less likely to arise. It is particularly preferred, although not essential, that an adaptor circuit provides a DMA capability for a single peripheral device connected thereto in a way that the DMA capability can be directly targeted at that individual peripheral device.

[0015] The present technique moves against the technical prejudice in the field which would normally hold that replicating DMA functionality at multiple points within a system would be wasteful of resources. However, the present technique recognises that the resources consumed are less than might be considered since the DMA managers provided for the peripherals can be relatively simple since they only need to deal with one or few peripheral devices and the overall benefits to system performance by removing potential bottlenecks are considerable. Furthermore, the signal routing difficulties associated with provision of centralised DMA units are reduced since the adaptors can be physically close to the peripheral devices with which they are associated. The technique also allows software compatibility with existing DMA architectures in which a main system DMA manager accepts DMA control information in the known way but, instead of performing the DMA function itself, forwards the control information to the appropriate DMA adaptor using DMA command signals. In this way advantages of the new system may be realised without needing to rewrite software drivers.

[0016] Whilst the system port could have a variety of different forms, the technique is particularly well suited to systems in which the system port on the adaptor circuit provides a system slave port for receiving data transfers and a system master port for issuing data transfers. It will be appreciated that a peripheral device normally only receives data transfers and accordingly a system port for such a device would normally only be provided with a system slave port. However, the addition of the direct memory access manager to the adaptor has the result that the adaptor can now initiate data transfers and accordingly a system master port is also added to issue such data transfers.

[0017] The peripheral port on the adaptor for coupling to the one or more peripheral devices is a peripheral master port since the data transfers are normally issued to peripheral devices rather than originating within peripheral devices. Thus, there would not normally be a requirement for a peripheral master port on the adaptor circuit.

[0018] As previously mentioned, an adaptor circuit could provide a peripheral port, or ports, interfacing with multiple peripheral devices downstream. The peripheral port could connect with a further level of interconnect structure for routing data transfers to selected ones of a plurality of downstream peripheral devices. However, the present technique is particularly well suited to embodiments in which the adaptor circuit is connected to a single peripheral device such that the direct memory access manager can be tailored to support direct memory access data transfers to and from that particular single peripheral device.

[0019] The impact of the adaptor circuit on system operation is advantageously reduced when the adaptor circuit is transparent to data transfers managed from outside the adaptor circuit when operating in the bypass mode.

[0020] The direct memory access manager advantageously has a priority level associated with the data transfers it manages and also may be provided with its own memory map for that direct memory access manager.

[0021] The direct memory access manager provided within the adaptor circuit will typically require some level of dynamic configuration during operation. One preferred way of achieving this is to add one or more direct memory access manager command signals to the signals passed to the adaptor circuit. These direct memory access manager command signals can then be used to trigger one or more associated data transfers to be used to configure the direct memory access manager concerned. The direct memory access manager configuration data can effectively be routed by addressing it to the associated peripheral device, or devices, and asserting the direct memory access manager command signals to indicate that it is DMA configuration data rather than data truly destined for the one or more peripheral devices to which it is being sent.

[0022] As an alternative mechanism, which may be desirable in other circumstances, the direct memory access manager within an adaptor circuit may have an associated portion of the memory address space dedicated to storing its configuration data and will read its configuration data from such memory space.

[0023] The configuration data can specify a variety of parameters associated with a direct memory access manager, but will typically include parameters specifying details of one or more data transfer operations to be performed autonomously by that direct memory access manager.

[0024] It will be appreciated that the system port could be connected to the plurality of further devices using various techniques. Preferred techniques include an interconnect matrix, such as, for example, the AXI bus system, as well as more traditional system buses.

[0025] Viewed from another aspect the present invention provides an adaptor circuit comprising:

[0026] a peripheral port means for connecting to at least one peripheral device means;

[0027] a system port means for connecting to a plurality of further devices means;

[0028] a direct memory access manager means for autonomously managing data transfers between one of said at least one peripheral device means coupled to said peripheral port means and at least one of said plurality of further device means coupled to said system port means; and

[0029] a bypass circuit means coupled to said system port means, said peripheral port means and said direct memory access manager means for in:

[0030] (i) a bypass mode, connecting said system port means to said peripheral port means such that data transfers managed from outside said adaptor circuit pass between said system port means and said peripheral port means; and

[0031] (ii) in a direct memory access mode, connecting said system port means to said direct memory access manager means and connecting said peripheral port means to said direct memory access manager means such that said direct memory access manager means autonomously manages data transfers between one of said at least one peripheral device means coupled to said peripheral port means and at least one of said plurality of further device means coupled to said system port means.

[0032] Viewed from a further aspect the present invention provides an integrated circuit comprising:

[0033] at least one peripheral device;

[0034] a plurality of further devices; and

[0035] at least one adaptor circuit having:

[0036] a peripheral port operable to connect to said at least one peripheral device;

[0037] a system port operable to connect to said plurality of further devices;

[0038] a direct memory access manager operable to autonomously manage data transfers between one of said at least one peripheral devices coupled to said peripheral port and at least one of said plurality of further devices coupled to said system port; and

[0039] a bypass circuit coupled to said system port, said peripheral port and said direct memory access manager and operable in:

[0040] (i) a bypass mode to connect said system port to said peripheral port such that data transfers managed from outside said adaptor circuit pass between said system port and said peripheral port; and

[0041] (ii) in a direct memory access mode to connect said system port to said direct memory access manager and to connect said peripheral port to said direct memory access manager such that said direct memory access manager autonomously manages data transfers between one of said at least one peripheral devices coupled to said peripheral port and at least one of said plurality of further devices coupled to said system port.

[0042] In the context of an integrated circuit including at least one of the adaptor circuits which provides its own direct memory access manager, it is preferred to additionally provide a traditional shared direct memory access controller which is able to autonomously manager data transfers on behalf of devices which do not have an adaptor including a dedicated direct memory access manager.

[0043] Viewed from a further aspect the present invention provides a method of managing data transfers, said method comprising the steps of:

[0044] connecting at least one peripheral device to a peripheral port of an adaptor circuit;

[0045] connecting a plurality of further devices to a system port of said adaptor circuit;

[0046] providing within said adaptor circuit a direct memory access manager operable to autonomously manage data transfers between one of said at least one peripheral devices coupled to said peripheral port and at least one of said plurality of further devices coupled to said system port;

[0047] providing a bypass circuit coupled to said system port, said peripheral port and said direct memory access manager; and

[0048] (i) in a bypass mode, connecting said system port to said peripheral port and managing data transfers from outside said adaptor circuit such that data transfers pass between said system port and said peripheral port; and

[0049] (ii) in a direct memory access mode, connecting said system port to said direct memory access manager, connecting said peripheral port to said direct memory access manager, and autonomously managing with said direct memory access manager data transfers between one of said at least one peripheral devices coupled to said peripheral port and at least one of said plurality of further devices coupled to said system port.

[0050] Viewed from a further aspect the present invention provides a computer program product carrying a computer program for controlling a computer to generate a configuration for an interconnect between at least one peripheral device and a plurality of further devices; said computer program comprising:

[0051] code responsive to a user input specifying that said at least one peripheral device is to be provided with direct memory access management capability to configure said interconnect to include an adaptor circuit dedicated to said at least one peripheral device and including a direct memory access manager operable to autonomously manage data transfers.

[0052] It is known to provide a variety of computer program tools for use in developing interconnections within modern systems which will typically include several peripheral devices and several further devices and that will have a complex set of requirements and interdependencies. The present technique of providing DMA support local to a peripheral device integrates particularly well with such tools since the DMA capability for a peripheral device may be specified to the computer program which will generate the configuration for the interconnect as a whole and this computer program tool can act upon such a user specification by interposing an adaptor having the above discussed DMA capability into the interconnect path between the peripheral and the one or more further devices.

[0053] The interconnect design tool can also conveniently be used to specify one or more parameters characterising the direct memory access management capability to be added. The system designer at the time they are specifying peripherals to be provided with ports to an interconnect will typically know the DMA requirements of those peripherals in the context of the system as a whole and thus will be able to readily specify these parameters to configure the adaptor being provided, for example the parameters may specify a buffer size to be provided, the priority level to be associated with a particular local direct memory access controller and/or the memory map for that direct memory access controller.

[0054] The use of computer tools to generate the interconnects is particularly useful when the interconnect is in the form of an interconnect matrix, such as an AXI interconnection matrix.

[0055] Viewed from a further aspect the present invention provides a signal interconnect for connecting at least one peripheral device, a plurality of further devices and at least one direct memory access manager, said signal interconnect including:

[0056] an address bus for transferring address signals specifying a target address for a data transfer;

[0057] one or more direct memory access manager command signals for triggering use of one or more associated data transfers to pass configuration data to configure a selected one of said at least one direct memory access managers as selected in dependence upon an associated target address on said address bus.

[0058] The provision of one or more direct memory access manager command signals within the signal interconnect allows for the distribution of direct memory access control configuration information through a system in a more uniform way utilising the existing interconnect structure which already connects to the DMA controllers concerned. This reduces the overhead associated with DMA control distribution.

[0059] This use of direct memory access manager command signals is particularly well suited to interconnection matrix systems where at least one direct memory access manager is provided within an adapter circuit local to a peripheral and the target address for a peripheral may be used to direct the direct memory access manager commands to that peripheral. The type of commands which may be passed include, for example, a number of data words to be included within a data transfer, a target address associated with a data transfer and a destination address associated with a data transfer (other different parameters may be passed in addition to or instead of these).

[0060] The above, and other objects, features and advantages of this invention will be apparent from the following detailed description of illustrative embodiments which is to be read in connection with the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

[0061] FIG. 1 schematically illustrates an integrated circuit including peripheral devices connected to an interconnect matrix via adaptor circuits which provide a DMA capability;

[0062] FIG. 2 schematically illustrates an adaptor circuit including a DMA controller;

[0063] FIG. 3 is a flow diagram schematically illustrating the portion of the operation of an interconnect generation tool related to specifying DMA capability for adaptor circuits used with peripheral devices;

[0064] FIG. 4 schematically illustrates an interconnect bus including a plurality of channels and provided with a DMA command signal for indicating that a DMA command is being passed; and

[0065] FIG. 5 illustrates a general purpose computer of a form which may be used to implement some of the present techniques.