In a large semiconductor memory having multiple memory modules that are addressable by a logical page address and a word address within each page, a technique for automatically testing the modules to establish a pool of good modules; then allocating each logical page of memory to a group of modules,...http://www.google.fr/patents/US5299202?utm_source=gb-gplus-shareBrevet US5299202 - Method and apparatus for configuration and testing of large fault-tolerant memories
Method and apparatus for configuration and testing of large fault-tolerant ...
