CURRENT GENERATING CIRCUIT
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates generally to a current generating (dynamic element matching) circuit, and more particularly to such a current generating circuit which is suitable for use in current switching for a digital-toanalog (D/A) converter.
2. Description of the Prior Art
First, a previously proposed current generating circuit 4, disclosed in Japanese Patent Publication No. 54-24098, will hereinafter be explained with reference to FIG. 1.
The current generating circuit 4 comprises a current dividing circuit 3 in a current mirror configuration which is formed of transistors Qi and Q2. Currents Ii and I2 passing through the transistors Qi and Q2 are respectively obtained by dividing a current 21 substantially by two, so that the currents Ii and I2 are substantially equal to each other. A pair of differential switching circuits la and lb, which form a current changeover circuit 2, respectively switch and deliver the currents Ii and I2 alternately to a pair of output terminals 25 T3 and T4. The differential switching circuit la is formed of a pair of transistors Q3 and Q4 which have their emitters connected with each other, and their connecting point is connected with the collector and the base of the transistor Qi. The other differential switching circuit lb is formed of a pair of transistors Q5 and Q_6 which have their emitters connected with each other, and their connecting point is connected with the collector of the transistor Q2.
The collectors of the transistors Q3 and Q5 are connected to the output terminal T3 in common, while the collectors of the transistors Q4 and Q_6 are to the other output terminal T4 in common. The output terminals T3 and T4 are grounded respectively through capacitors Cx and Cy constituting low pass filters.
The input terminals Ti and T2, for switching, are fed with a pair of opposite-phased switching signals Ei and E2 with a predetermined frequency. The switching input terminal Ti is connected to the bases of the transistors Q3 and Q6 in common, while the other switching 45 input terminal T2 is connected to the bases of the transistors Q4 and Q5 in common.
Next, the operation of the current generating circuit 4 will be explained. When the switching signal Ei supplied to the input terminal Ti is at a high level, the switching signal E2 supplied to the input terminal T2 is at a low level, so that the transistors Q3 and Q.6 are turned on while the transistors Q4 and Q5 are turned off. Therefore, the current Ii from the current dividing circuit 3 is delivered to the terminal T3 and the current I2 is delivered to the terminal T4, respectively.
When the switching signal E2 supplied to the switching input terminal T2 is at the high level, the switching signal Ei supplied to the input terminal Ti is at the low level, so that the transistors Q4 and Q5 are turned on while the transistors Q3 and Q6 are turned off. Therefore, the current Ii from the current dividing circuit 3 is delivered to the terminal T4 and the current I2 is delivered to the terminal T3, respectively.
Thus, the output terminal T3 is alternately fed with the currents Ii and I2, while the output terminal T4 is alternately fed with the currents I2 and Ii. These currents I2 and Ii are averaged by the capacitors Cx and Cy
constituting the low pass filters, so that both of the output terminals T3 and T4 are equally fed with a current I (I=(Ii+l2)/2), as a result. In other words, the current generating circuit 4 can provide at its two output terminals the output current I which is derived by accurately dividing the input current 21 supplied thereto by two.
Let it now be assumed that the current generating circuits 4a, 46 and 4c, each being explained with reference to FIG. 1 as disclosed in Japanese Patent Publication No. 54-24098, are connected upward in a piling manner as shown in FIG. 2. The current generating circuit 4a at the first stage is disposed to divide the input current 21 by two to obtain the two output currents, I and I, one of which is delivered to the output terminal T4, and the other of which is supplied to one input terminal of the current generating circuit 4b at the next stage.
Then, the current generating circuit 4b is disposed to divide the input current I by two to obtain two output currents 1/2 and 1/2 , one of which is outputted to an output terminal T5, and the other of which is supplied to one input terminal of the current generating circuit 4c at the third stage.
By repeating the above operation, the current generating circuit 4c at the third stage derives a current 1/4 at its output terminal T6. Incidentally, reference letters T3, T3' and T3" designate the other output terminals of the current generating circuits 4a, 4b and 4c, respectively.
If each of the output currents delivered to the output terminals T4, T5 and T6are controlled independently by different switches which are turned on and off in accordance with binary combinations of a 3-bit digital signal, a current generator type D/A converter can be formed.
The current generating circuit 4 shown in FIG. 1 can derive the substantially equal current at the output terminals T3 and T4by averaging the input currents Ii and I2 supplied to the differential type switching circuits la and lb. However, if the current generating circuits are arranged in multi-stage as shown in FIG. 2, to form e.g. an n-bit D/A converter, the total number of the transistors Q3 and Q4, for example, in the differential switching circuit la is increased by n times, so that the voltage necessary to operate all these transistors Q3 and Q4 or the like becomes higher as the bit number of the D/A converter is increased.
To solve the above-mentioned problem, Japanese Patent Publication No. 57-31809 discloses to derive from the single current generating circuit 4 the output currents 1,1/2,1/4 ... which have been delivered one by one from the current generating circuits 4a, 4b, 4c . .. That is, the single current generating circuit provided with a plurality of output terminals for deriving a plurality of output currents, for example I and 1/2, is disclosed. The construction shown in this document can reduce the number of the current generating circuits 4a, 4b, 4c . . . which are piled by connecting in multiple stages, as shown in FIG. 2, thereby making it possible to reduce the source voltage.
A single-stage current generating circuit equivalent to the above-mentioned two-stage current generating circuit and the operating waveforms thereof is explained below with reference to FIGS. 3 and 4, by using the principle of Japanese Patent Publication No. 57-31809.
In FIG. 3, reference numeral 4 designates an overall current generating circuit in which an input terminal
