1
RADIATION-HARDENED
SILICON-ON-INSULATOR CMOS DEVICE,
AND METHOD OF MAKING THE SAME
5
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention generally relates to semiconductor devices and processes and more specifically to a method of fabri- 10 eating and processing P-channel transistors in silicon layers formed on insulating substrates to obtain devices having high degrees of total dose radiation hardness.
2. Description of Related Art
Metal oxide semiconductor (MOS) technology is virtually :5 the standard for digital circuits used in computers and telecommunication devices today Increasingly, CMOS (complementary MOS) technology is utilized in these applications. CMOS technology incorporates both N-channel MOS and P-channel MOS transistors in the same monolithic 20 structure.
"Radiation hardness" refers to the ability of a semiconductor device to withstand ionizing radiation without significant alteration of its electrical characteristics. A semiconductor device is said to be radiation hardened (rad-hard), 25 radiation tolerant, or radiation resistant if it can continue to function within specifications after exposure to a specified amount and type of radiation. Semiconductor devices can be damaged or destroyed by the effects of ionizing radiation from natural and man-made sources. Radiation changes the 30 electrical properties of solid state devices, leading to possible failure of any system incorporating them. Applications for radiation hardened semiconductor devices include use in harsh environments such as outer space, nuclear reactors,
35
and particle accelerators. Additionally, improved radiation hardness is growing increasingly useful as semiconductor processing employs more processes that generate radiation. For example, processing techniques such as reactive ion etching and plasma etching introduce some radiation damage into the fabricated semiconductor structure. 40
The effect of ionizing radiation on MOS transistors is well known. The dominant effect is the charging of insulating layers adjacent to the semiconductor regions as a result of exposure to ionizing radiation. These charging effects have 4J been widely studied, and mathematical models have been developed which provide a reasonable amount of predictive capability of the effect of ionizing radiation on the operation of an MOS device.
The induced charges can be categorized as one of two 50 principal types, fixed oxide charges and interface state charges. The first type, fixed oxide charges, are incapable of exchanging charges with the semiconductor, and hence their charge density is insensitive to the position of the Fermi level in the adjacent semiconductor region. The second type 55 is due to interface state charges which do exchange charges with the semiconductor layer and hence are sensitive to the position of the Fermi level in the adjacent semiconductor material. Both types of charges may or may not be produced in significant numbers as a result of the device being 60 exposed to ionizing radiation. The two types of charges may occur separately or together.
There are several factors that determine the sensitivity of an MOS device to ionizing radiation exposure. Some of these factors include the dimensions of the device (W/L), the 65 doping levels used in the construction of the device, the thicknesses of the insulating layers, and the electric fields
2
across various regions of the device during the period of time that it is being exposed to the ionizing radiation environment.
In an effort to improve the performance of MOS devices, the art has focused on Semiconductor-On-Insulator (SOI) technology. In SOI technology, the devices are formed in a monocrystalline semiconductor layer, which is formed on an insulating layer which provides device isolation. While both conventional bulk CMOS devices and SOI CMOS devices may show degradation as a result of exposure to ionizing radiation, in SOI devices there are additional insulating layers (compared to bulk transistors) that can become charged as a result of radiation exposure.
It is well known that the so-called back interface of an SOI transistor can be very sensitive to ionizing radiation. In general, the charges that result are positive fixed charges in the back insulating layer. Since a positive oxide charge images a negative charge in the adjoining silicon region, the effect of such positive charge on the device operation can be readily understood.
In particular, for an N-channel transistor, the effect of such positive charge is to induce electrons at the back interface between the semiconductor layer and the insulating substrate. This will result in current flow between the source and drain of the transistor, even without the presence of a gate bias. This current is widely called "back channel" current to denote the fact that it is flowing near the back interface and is not capable of being controlled by the MOSFET gate. Similarly, it can be seen that positive charges in the back interface of a P-channel device will image negative charges in such a device, but that these negative charges will not result in any current flow in a P-channel transistor. Conversely, negative charges in such a back insulator image positive charges into the adjacent semiconductor region, causing current flow in a PMOS device, but no current flow in an NMOS device.
Previously, silicon-on-insulator (SOI) has been used for high performance microelectronics. The desirability of SOI devices for applications requiring radiation hardness is wellrecognized. Fabrication of devices on an insulating substrate requires that an effective method for forming silicon CMOS devices on the insulating substrate be used. The advantages of using a composite substrate comprising a monocrystalline semiconductor layer, such as silicon, epitaxially deposited on a supporting insulating substrate, such as sapphire, have been well-recognized. These advantages include the substantial reduction of parasitic capacitance between charged active regions and the substrate and the effective elimination of leakage currents flowing between adjacent active devices. This is accomplished by employing as the substrate an insulating material, such as sapphire (A1203), spinel, or other known highly insulating materials, and providing that the conduction path of any interdevice leakage current must pass through the substrate.
An "ideal" silicon-on-insulator wafer may be defined to include a completely monocrystalline, defect-free silicon layer of sufficient thickness to accommodate the fabrication of active devices therein. The silicon layer would be adjacent to an insulating substrate and would have a minimum of crystal lattice discontinuities at the silicon-insulator interface. Early attempts to fabricate this "ideal" silicon-oninsulator wafer were frustrated by a number of significant problems, which can be summarized as (1) substantial incursion of contaminants into the epitaxially deposited silicon layer, especially the p-dopant aluminum, as a consequence of the high temperatures used in the initial epi
