SYSTEM TECHNIQUE FOR DETECTING
SOFT ERRORS IN STATICALLY COUPLED
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to circuits for detecting error transients in logic circuits due to atomic events or other non-recurring noise transients.
2. Background Description
Statically (DC) coupled Complementary Metal Oxide Semiconductor (CMOS) logic has been employed in the vast majority of logic applications for the last fifteen years. It has enjoyed this pre-eminence as a result of an unusually broad set of highly desirable features including very low power consumption, high performance and rugged resistance to 15 external noise sources. Until very recently this has included absolute resistance to atomic events like the emission of alpha particles from near proximity metals and the incidence of cosmic rays from just about anywhere.
Rapid advances in lithography have allowed circuit node 20 features to shrink in area about a factor of two every two years. Node capacitance has shrunken almost as fast. With the advent of 0.2 micron lithography, small lightly loaded nodes are vulnerable to error transients. The vulnerability of the computation is a more complex matter. To actually 25 corrupt the computation, the atomic event, whether alpha or cosmic in origin, must impinge on one of these lightly loaded nodes within a time window such that the error transient is likely to be latched into a register. Error transients which are too short to propagate to the next latch or 30 which occur in plenty of time for the logic levels to recover after the transient will not be captured by the latches. As lithography features shrink further, more and more of these error transients will impinge upon vulnerable nodes and be captured as bona-fide soft errors. 35
Earlier work fails to correct the problem. The atomic event induced soft error problem was first detected and eventually corrected in memory. Small Static Random Access Memory (SRAM) and Dynamic Random Access Memory (DRAM) cells have inherently small lightly loaded 40 circuit nodes and thus exhibited early vulnerability to this problem. The problems of detection and ultimately correction were solved in a straight forward manner using parity for error detection and multidimensional parity with error correction codes. This early success lead to much research in 45 an effort to extend code detection to logic. Researchers today agree this approach has failed. The codes devised are simply too complex and too specialized for implementation in general purpose logic.
Abrute force solution is unattractive. We could, of course, 50 simply pad all vulnerable circuit nodes with extra capacitance. This "solution" stands in direct opposition to one of the principle motivations of finer lithography. That is to improve circuit and system performance. In the last three technology generations, the effective transconductance at 55 nominal power supply has not changed significantly; rather, improved performance has been largely achieved by lowering node capacitance and decreasing nominal power supply. Both factors increase node vulnerability. Charge or discharge transients from atomic events can vary tremendously. 60 However, a given event appears as a fixed charge or discharge on the affected node, independent of the node size or voltage.
SUMMARY OF THE INVENTION 65
According to the invention, there is provided a first circuit coupled to a data line for sensing a first signal on the data
line at a first point in time (Tl) and a second circuit coupled to the data line for sensing the first signal on the data line at a second point in time (T2) such that a time difference between Tl and T2 is small enough so that the first signal is still present on the data line in the absence of a perturbation event and such that the time difference between Tl and T2 is large enough so that any such perturbation event is resolved. A compare circuit coupled to the first and second circuits compares the sensing of the first signal by the first and second circuits, and generates an error signal in response to a non-compare.
BRIEF DESCRIPTION OF THE DRAWINGS
The foregoing and other objects, aspects and advantages will be better understood from the following detailed description of a preferred embodiment of the invention with reference to the drawings, in which:
FIG. 1 is a block diagram of a simplified logic system which illustrates the problem of the prior art;
FIG. 2 is a block diagram of the logic system of FIG. 1 modified to include the present invention;
FIG. 3 is a block and logic diagram of a single master and slave pair with sample and hold circuits according to the teaching of the invention;
FIGS. 4A and 4B are, respectively, a circuit diagram and a block diagram of examples of sample and hold circuits suitable to the practice of the invention;
FIGS. 5A and 5B are block and logic diagrams similar to FIG. 3 showing an extension of the invention to included slave latches; and
FIGS. 6A and 6B are block and logic diagrams showing, respectively, a hazard and the solution of a potential race condition.
DETAILED DESCRIPTION OF A PREFERRED
EMBODIMENT OF THE INVENTION
Referring now to the drawings, and more particularly to FIG. 1, there is shown a simplified logic system represented by a typical combinatorial logic block 10 of about eight stages followed by a master and slave set of latches (registers) 12 and 14. In this example, results of previous calculations are recirculated and combined with new data for subsequent calculations in multiplexer 16. A transient error at a vulnerable node during a critical time window is captured by a master latch 12 and subsequently fed to a slave latch 14. The erroneous data then is constantly recirculated through the logic block corrupting all future calculations.
FIG. 2 shows this same simplified logic system of FIG. 1 modified to include the invention. In particular, the unique circuits of this invention are illustrated in general block form as block 20. These circuits, described in more detail with reference to FIG. 3 below, are connected to outputs of the combinatorial logic block 10 and outputs of the master latches 12. The circuits in block 20 comprise a first circuit coupled to a data line of the combinatorial logic 10 for sensing a first signal on the data line at a first point in time (Tl) and a second circuit coupled to the corresponding data line of the master latches for sensing the first signal on the data line at a second point in time (T2) such that a time difference between Tl and T2 is small enough so that the first signal is still present on the data line in the absence of a perturbation event and such that the time difference between Tl and T2 is large enough so that any such perturbation event is resolved. The outputs of the first and second circuits are input to a compare circuit for comparing