VIRTUAL PHASE CHARGE TRANSFER DEVICE
This invention relates to semiconductor charge transfer devices and more particularly to a buried-channel, 5 Uniphase, charge coupled device (CCD) wherein a portion of each cell includes an inversion layer at the semiconductor surface that functions as a virtual electrode, shielding that region from any gate-induced change in potential. 10
Uniphase CCD's have been well known for several years. See for example U.S. Pat. No. 4,047,215 issued to Robert Charles Frye et al, showing a uniphase charge coupled device including a continuous conductive gate layer over the signal channel of the CCD. The Frye et 15 al device is a surface channel device, i.e., the signal charge packets are propagated along the surface of the semiconductor. The principal disadvantage of known uniphase CCD devices is their small charge handling capacity and the relatively large clock pulse amplitude 20 requirement, compared to the more common multiphase CCD's.
A more recent addition to the family of charge transfer devices is the buried-channel CCD wherein the mobile charge is stored and transported in an induced 25 channel within the bulk of a thin semiconductor layer. As opposed to the more common surface-type CCD, a buried-channel CCD avoids the trapping effects normally associated with the oxide-silicon interface, thereby improving the charge transfer efficiency. Also, 30 the absence of any interface carrier scattering increases charge transfer mobility. Higher operating frequencies are therefore realized. For a more complete description, see Hamdi El-Sissi et al, "One Dimensional Study of Buried Channel Charge Coupled Devices", I.E. EE. 35 Transactions on Electron Devices, Vol. ED. 21, No. 7, pages 437-447 (July 1974). A buried-channel, uniphase CCD is shown in U.S. Pat. No. 4,065,847.
It is an object of the present invention to provide a single phase buried-channel CCD which is comparable 40 in performance to multiphase CCD's, while retaining all the advantages of singlelevel structure.
One aspect of the present invention is embodied in a uniphase CCD structure having either a continuous or patterned single conductive layer over a multiple-ceil 45 signal channel, each cell of which includes four regions (I, II, III, IV) of different impurity profiles implanted or diffused at the proper depth within the semiconductor surface. The characteristic impurity profiles within each region determine the maximum potential gener- 50 ated therein for the gate "on" and gate "off' conditions.
Regions III and IV of each cell include an inversion layer at the semiconductor surface to shield that portion of the cell from any gate-induced change in potential. Clocking the gate causes the potential maxima in re- 55 gions I and II to cycle above and below the fixed potential maxima in regions III and IV. Directionality of charge transfer is thereby achieved, since the potential maximum for region II remains greater than for region I, and region IV greater than region III, for both gate 60 conditions.
The device further includes a uniform, adherent insulation layer between the semiconductor surface and the uniphase electrode. Signal input means and signal output means are provided, in addition to means for supply- 65 ing a uniphase clock pulse to the electrode.
Another aspect of the invention is embodied in a process for fabrication of a device including four se
quential stages of ion implantation. More specifically, the process begins with a step of selectively implanting a first does of donor impurity ions in an oxide layer covering an N-type channel in a silicon body of P-type conductivity, to establish a forst source of impurity for subsequent use in fixing the profile for region II of each cell. A doped polysilicon gate electrode is then deposited and patterned on the oxide layer covering the channel regions at locations to become regions I and II of each cell. The polysilicon is then used as a mask for removing the oxide over channel regions to become regions III and IV of each cell. Photoresist is then patterned to cover region III, while additional donor impurities are implanted in region IV of each cell location. The photoresist is stripped, and more donor ions added for cell regions III and IV. A heat treatment follows, to anneal implant damage and diffuse impurities, both from the oxide into region II, and to increase the depth of impurities in regions III and IV. Finally, acceptor impurities are placed in regions III and IV at a more shallow depth than the new depth of donors therein, to complete the necessary profiles within each cell.
An alternative process sequence is provided, including two donor ion implantations or diffusions, followed by two acceptor ion implantations or diffusions. The profile of region II of each cell is determined by the buried channel doping itself, since no modification thereof is required for purposes of the invention. A continuous gate electrode is provided, as distinguished from the patterned gate of the previously stated embodiment.
FIG. 1 is a greatly enlarged perspective view with cutaway portions in cross section, taken both longitudinally of and normal to the channel region of a CCD structure according to the invention.
FIGS. 2a-2d are graphs showing the potential profiles for each of the four regions within each cell, for the gate "off condition, and for the gate "on" condition.
FIGS. 3a-3b illustrate the impurity concentration profiles for each of the four regions within each cell of the device of FIG. 1.
FIG. 4 is a diagram of the potential wells associated with operation of the device of the invention.
FIGS. Sa-Se illustrate a process sequence for fabrication of an embodiment of the invention.
FIGS. 6a-6e illustrate a second process sequence for fabrication of another embodiment.
FIG. 7 is a plot of the maximum potential for each region of the cell, as a function of gate voltage.
FIG. 1 is a diagramatic view showing one cross-section along the channel of a uniphase CCD structure embodying the invention, and a second cross section normal to the first. The device channel is formed in P-type silicon substrate 11 having a doping density substantially greater than 1 X 1015cm~3 and preferably greater than lxl015cm-3 but not greater than 1018cm-3. The upper surface of substrate 11 as seen in FIG. 1 is covered by insulating layer 12, typically of silicon dioxide, having uniform thickness extending along the length of an N-type channel region. A continuous gate electrode 13 extends along the length of the channel and is connected to a clock pulse source. Spaced along the length of the channel are a plurality of cells, each of which includes a P-type inversion layer 14 at the surface of regions III and IV of each cell, which acts as a virtual electrode, shielding that portion of each cell from any gate-induced change in potential. Just below the inversion layer the buried channel potential
