MULTI-FORMAT REDUCED MEMORY
MPEG DECODER WITH HYBRID MEMORY
CROSS-REFERENCE TO RELATED APPLICATIONS 5 This application comprises a continuation-in-part patent application from commonly assigned, co-pending U.S. patent application by Cheney et al. entitled "Multi-Format Reduced Memory MPEG-2 Compliant Decoder," Ser. No. 08/958,632 Oct. 27, 1997, the entirety of which is hereby 10 incorporated herein by reference. Further, this application is related to commonly assigned, co-pending U.S. patent application by Buerkle et al., entitled "Compression/ Decompression Engine For Enhanced Memory Storage In MPEG Decoder," Ser. No. 08/971,438, which is also hereby 15 incorporated herein by reference in its entirety.
The present invention relates generally to digital video signal processing, and more particularly, to a hybrid soft- 20 ware and hardware addressing of external memory in a video decoder system allowing multi-format and decimated data storage in memory.
BACKGROUND OF THE INVENTION 25
Several international standards for the compression of digital video signals have emerged over the past decade, with more currently under development. These standards apply to algorithms for the transmission and storage of 3Q compressed digital video in a variety of applications, including: video-telephony and teleconferencing; high quality digital television transmission on coaxial and fiberoptic networks, as well as broadcast terrestrially and other direct broadcast satellites; and in interactive multimedia products 3J on CD-ROM, Digital Audio Tape, and Winchester disk drives.
Several of these standards involve algorithms based on a common core of compression techniques, e.g., the CCITT (Consultative Committee on International Telegraphy and 40 Telephony) Recommendation H.120, the CCITT recommendation H.261, and the ISO/IEC MPEG-1 and MPEG-2 standards. The MPEG algorithms have been developed by the Moving Picture Experts Group (MPEG), part of a joint technical committee of the International Standards Organi- 45 zation (ISO) and the International Electrotechnical Commission (IEC). The MPEG Committee has been developing standards for the multiplexed, compressed representation of video and associated audio signals.
The MPEG-2 standard describes an encoding method that 50 results in substantial bandwidth reduction by a subjective lossy compression followed by a lossless compression. The encoded, compressed digital data is subsequently decompressed and decoded in an MPEG-2 compliant decoder. The MPEG-2 standard specifies a very high compression tech- 55 nique that achieves compression not achievable with intraframe coding alone, while preserving the random access advantages of pure intraframe coding. The combination of frequency domain intraframe encoding and interpolative/ predictive interframe encoding of the MPEG-2 standard go results in a balance between intraframe encoding and interframe encoding.
The MPEG-2 standard exploits temporal redundancy for motion compensated interpolative and predictive encoding. That is, the assumption is made that "locally" the current 65 picture can be modeled as a translation of the picture at a previous and/or future time. "Locally" implies that the
amplitude and direction of the displacement are not the same everywhere in the picture.
The MPEG-2 standard further specifies predictive and interpolative interframe encoding and frequency domain intraframe encoding. It has block-based motion compensation for the reduction of temporal redundancy and discrete cosine transform based compression for the reduction of spatial redundancy. Under MPEG-2, motion compensation is achieved by predictive coding, interpolative coding, and variable length coded motion vectors. The information relative to motion is based on a 16x16 array of pixels and is transmitted with the spatial information. It is compressed with variable length codes, such as Huffman codes.
Video decoding in accordance with the MPEG-2 standard is described in greater detail in commonly assigned United States Letters Patent No. 5,576,765, entitled "Video Decoder" which is hereby incorporated herein by reference in its entirety.
Video decoders are typically embodied as general or special purpose processors and memory. For a conventional MPEG-2 decoder, two decoded reference frames are typically stored in memory at the same time. Thus, the cost of memory can often dominate the cost of the decode system. For example, an MPEG-2 video decoder might employ 2 MB or more of external memory, which generally comprises Dynamic Random Access Memory (DRAM). External memory is used for various data areas, or buffers such as frame buffers.
In practice, the MPEG-2 video decoder is typically limited to 2 MB of external memory in order to minimize cost of the end product. The decoder must perform all of its functions within this limitation. For example, of particular importance is enabling output for both the European market which utilizes the PAL standard of 576 video scan lines and the U.S. market which utilizes the NTSC standard of 480 video scan lines.
The MPEG-2 decompressed video data buffers, also called frame buffers, consume the largest part of external DRAM, therefore they are a prime candidate for memory reduction/compression. However, because the frame buffers contain final pixel display and MPEG reference data, any storage reduction technique must retain high video fidelity in the frame buffers.
Another obstacle faced in video compression/ decompression is being able to transform pictures between different sized screens. For example, a motion picture screen is in 16:9 format, while a television screen is in 4:3 format. As a result, a method must be provided to convert between 16:9 and 4:3 form factors. This need is discussed in the above-incorporated, pending U.S. Application entitled "Multi-Format Reduced Memory MPEG-2 Compliant Decoder," which is described further herein.
In view of the above, and in order to establish commercial advantage, an enhanced technique for a digital video decoder is desired for generating read and write addresses to external memory allowing multi-format and reduced video data storage. The present invention addresses this need.
DISCLOSURE OF THE INVENTION
Briefly summarized, the invention comprises in one aspect an address generation engine for a digital video decoder unit coupled to memory. The address generation engine includes a processor and address generation hardware. The processor is coupled to access an encoded video signal to be decoded by the digital video decoder unit, and includes microcode for deriving from the encoded video