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LOW SPEED SERIAL BUS PROTOCOL AND
CIRCUITRY
This is a divisional of application Ser. No. 08/578,168 filed Dec. 29, 1995, now U.S. Pat. No. 5,819,051. 5
BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates to a serial bus capable of communicating with many serial bus devices, and more particularly 10 to a protocol and latency reduction circuit for communicating with low speed serial bus devices.
2. Description of the Related Art
Computer systems are becoming ever more powerful with 15 each passing moment. Many new advanced bus structures such as the PCI or Peripheral Component Interchange bus have been developed to allow greater performance of the computer system. Additionally, new devices and uses are being developed for the computer systems. In the past the 2Q computer has been essentially a stand-alone device or networked with other computer systems. However, today the modern personal computer is becoming a much more connected and multimedia oriented system. For example, now high speed video and audio functions are becoming com- 2J monplace and the integration with the telephone system has already begun.
However, many of these new features are well below the ultimate bandwidth or capability of the advanced buses such as the PCI bus. Therefore, it is not efficient to connect each 30 one of the new functions and devices to the PCI bus directly, as this would impact bus loading and greatly increase overall costs. Additionally, many of these new functions are essentially serial in nature, with the data transferred in a bit stream rather than over a parallel bus structure. This is provided for 35 many reasons, such as reduced wiring costs, and can be done because of the lower data rates which are required.
Therefore, it has been proposed to develop a serial bus architecture to connect all of these various lower bandwidth devices. The serial bus is organized with a host controller 40 having a series of ports, which can then be connected either directly to devices or functions or to further hubs which have below them further devices or functions. A hub or the host controller may in addition incorporate functions if desired. In this manner a tree structure can be developed to allow a 45 reasonable number of functions or devices to be attached to the serial bus system. The host controller connects to a bus in the computer system, for example the PCI bus, through the host controller. By having the host controller act as a concentrator, only a single connection to the PCI bus is 50 necessary. The connection is better able to utilize the performance of the PCI bus without requiring numerous connections.
The host controller, each hub, and each function or port contain particular control registers for doing set up and 55 initialization operations. In addition, four basic types of data transfer are defined in the serial bus system. The first type is isochronous, which is effectively a continuous real time transfer, such as telephony information or audio information. The second type is asynchronous block transfers, such 60 as printer operations and conventional serial port operations, while the third type is asynchronous interactive device transfers, such as keyboard, mouse, pointing device, pen interfaces, and the configuration and status information, generally referred to as the control information, of the 65 various devices. The fourth type is a polling or interrupt type which is used to periodically access a device to determine if
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it has any status change to report back to the controlling software of the device.
Information is broadcast over the serial bus system from the host controller in a series of packets, with the host controller acting as the bus master and hubs and devices only responding upon request or polling access of the host controller. The packet types include data packets, token packets for use from host to device, a handshake packet and a special control packet. Data packets are the isochronous, asynchronous block, and asynchronous control types. Token packets allow transfer of data packets. Handshake packets are used to perform a ready handshake after transfer of a data or control packet to acknowledge successful receipt or indicate unsuccessful receipt. Special control packets are used for logical reset and status request transfers. Each function or device has a logical address.
Each device and port on a hub or the host controller includes the capabilities to handle the low level bus transfer protocol between the particular node of the appropriate hub and the device itself. Thus, a relatively simple transfer protocol, with a limited number of packet types is defined.
The hubs act as wiring concentrators and enable the attachment of multiple serial bus devices to the serial bus. A hub repeats incoming traffic from any enabled port by broadcasting the traffic transparently to all other enabled ports on the hub. As a result, the tree structured interconnect topology appears as a flat "virtual bus" with no store-andforward type delays.
The functions connected to the hubs have various bus bandwidth requirements. While some devices, such as video and audio, may have relatively high bus bandwidth requirements, other devices, such as mice and keyboards, may have very low data bandwidth requirements. As a result, these low speed functions do not need the same interface requirements as a faster function, not only for performance reasons but also for cost reasons. Therefore, it would be desirable to have an interface compatible with the serial bus, but operating at a slower rate and costing much less to implement.
SUMMARY OF THE PRESENT INVENTION
A low speed serial bus portion according to the present invention utilizes circuitry and a low speed serial bus protocol to provide an inexpensive alternative to the standard serial bus interface. The serial bus comprises a host controller communicating in a tree-like structure with numerous devices, hubs and functions. Hubs, having ports, are used to provide additional fan-out to more functions or devices. The connection between a low speed function and a port establishes a low speed interface. In the preferred embodiment, circuitry on an upstream hub senses the low speed function and modifies its signaling from conventional serial bus signaling to signaling according to the present invention.
A low speed function connected to the serial bus receives a clock signal from the hub. Data is received by the low speed function from the hub device over a bidirectional data line. The low speed function also provides data to the hub over the same data line. The low speed function may utilize a 5V power line, provided by the serial bus, without a regulator by adapting a 5V data signal from the low speed function to a 3.3V compatible data signal by a resistor divider circuit.
In the preferred embodiment, the low speed portion of the serial bus utilizes a two-wire protocol for communications between the low speed function and the hub. A data transfer
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has a starting and ending handshaking protocol for acknowledging transfers. Terminations and retries are also supported.
As the low speed serial bus portion transfers are performed at a slower clock frequency, a circuit is provided in 5 the hub for reducing latency by making more bandwidth available on the serial bus and reducing costs in the function, as compared to a full serial bus interface. Data transfers between the low speed function and the hub are serially registered so that when the serial register is full, a transfer 1° from the hub to the host controller will be fast and efficient.
BRIEF DESCRIPTION OF THE DRAWINGS
A better understanding of the present invention can be obtained when the following detailed description of the preferred embodiment is considered in conjunction with the following drawings, in which:
FIG. 1 is a block diagram of a computer system incorporating a serial bus system according to the preferred 2Q embodiment;
FIG. 2 is a detailed block diagram illustrating a connected hub according to the preferred embodiment;
FIG. 3 is a schematic diagram of the serial bus wiring and buffer configuration according to the prior art; 25
FIG. 4 is a schematic diagram of a low speed serial bus wiring portion and driver circuitry according to the preferred embodiment;
FIG. 5 is a block diagram of low speed data buffer circuitry according to the preferred embodiment;
FIG. 6 is a timing diagram according to the preferred embodiment illustrating a low speed serial bus portion in which permission is granted, but no transfer occurs;
FIG. 7 is a timing diagram according to the preferred 35 embodiment illustrating the low speed serial bus portion in which: permission is granted, the function begins a data transfer, and the transfer is aborted by the hub; and the end of a transfer in which the completed transfer is acknowledged by the hub; and 40
FIG. 8 is a timing diagram according to the preferred embodiment illustrating the low speed serial bus portion in which: permission is not granted, the hub begins a data transfer, and the transfer is aborted by the function; and the end of a second transfer in which the completed transfer is 45 acknowledged by the function.
DETAILED DESCRIPTION OF THE
PREFERRED EMBODIMENT
Referring now to FIG. 1, the computer system C accord- 50 ing to the preferred embodiment is generally shown. The computer system C includes a processor 100 such as a Pentium® or 486 processor by Intel or their equivalents. It is understood that other processors could of course be utilized. The processor 100 is connected to a second level or 55 L2 cache 102 and to a memory and L2 cache controller and PCI bridge 104 and address and data buffer 106. The main memory 108 of the computer system C is connected between the memory and L2 cache controller 104 and the address and data buffer 106. It is understood that the processor 100, 60 cache 102, memory and cache controller 104, address and data buffer 106 and main memory 108 form the processor system and processor to PCI bus bridge according to a PCI system. It is understood of course that alternate processor systems and high speed bus architectures could be utilized if 65 desired. Further, the address buffering could be included in the PCI bridge 104.
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The PCI bridge 104 and address and data buffer 106 are connected to a PCI bus 110 which performs the high speed high performance back bone of the computer system C. A PCI to ISA (Industry Standard Architecture) bridge 110 is connected between the PCI bridge 110 and an ISA bus 114. Afloppy disk controller 116 is connected to the ISA bus 114, as is the system ROM (read only memory) 118. Additionally, there may be a plurality of ISA slots connected to the ISA bus 114 for receiving interchangeable cards.
The majority of the devices are connected to the PCI bus 110. For example, a SCSI or IDE (Intelligent Drive Electronics) controller 122 is connected to the PCI bus 110 and to the associated disk drives and other devices (not shown). A network interface card (NIC) 124 is also connected to the PCI bus 110 to allow high performance network connections. Further, a video graphics system 126 is connected to the PCI bus 110 and to an associated monitor 128. A fax/modem DSP (digital signal processor) 138 can also be connected to the PCI bus 110 for fax and modem data processing. As noted, this is an exemplary computer system architecture and is provided for explanation, variations being readily apparent to one skilled in the art.
Of interest to the present description, a serial bus host controller 130 is also connected to the PCI bus 110. The serial bus host controller 130 of the illustrated embodiment acts as both a host controller and a hub, with various hubs and functions connected to the host bus controller 130. For example, a printer 132 is connected to one port of the serial bus host controller 130, while an expansion hub 134 is connected to a second port. The expansion hub 134 provides further expansion capabilities, such as connecting to a low speed function 152 according to the present invention. This connection will be described in more detail below. A telephony interface 136 containing the necessary CODEC and DAA components is connected to a third port and also receives a telephone line. The telephone line can be any of the available types such as an analog line, an ISDN line, a PBX connection and so on.
In the illustrated embodiment, the monitor 128 further acts as a hub and as a node. The monitor 128 is thus connected to one port of the serial bus host controller 130. The node or device function of the monitor 128 allows configuration of the monitor 128 independent from the high speed data utilized in the video system 126. The monitor 128 preferably acts as a hub because of the conventional physical arrangement of a modern computer system. Preferably, the system unit which contains the other devices is located under the desk or in a relatively remote location, with only the monitor 128, a keyboard 140, a pointing device such as a mouse 142 or pen 144, a telephone handset 146, and microphone and speakers relatively accessible to the user. As the monitor 128 effectively forms the central core of this unit, it is logically a proper location for a hub. The telephone handset 146 could be connected to one port of the monitor hub to receive digitized analog information either directly from the telephony interface 136 or as otherwise available, such as from an answering machine or voice mail function. The microphone is part of audio input circuitry 148 which is connected to a second port of the monitor hub, while audio output circuitry 150 contains the speakers used for audio output. The keyboard 140 further acts as a hub itself and a node, in that it is connected to the monitor hub but further contains ports to connect to the mouse 142 and a pen or stylus pointing device interface 144. This further physical connection is appropriate as those are the primary input devices and they are in most cases generally relatively near the keyboard 140 to ease use of operation. In all cases, each
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