FIG. 5 is a block diagram of the secondary queue, pleted for all output processing units within the time allotted
registers in a FIFO for representing each cell in the queue, to one cell cycle of the fastest associated input link 14 and
a search circuit for selecting cells from the queue which output link 30 of the switch. U.S. Pat. No. 5,455.825
match a particular virtual channel, and a bus read circuit for describes the queue and search system in more detail,
reading out information from the queue; 5 Referring now to FIG. 2. the subject invention uses a dual
FIG. 6 is a schematic diagram of four queue entries input queue architecture 18A in connection with a controller 22A.
to the search circuit in FIG. 5; The remaining structure of the switch 10A is generally the
same as switch 10 as shown in FIG. 1. More details of the
DETAILED DESCRIPTION dual queue architecture 18A and the controller 22A will now
Referring now to FIG. 1, an ATM Switch 10 is provided. 10 be described hi connection with FIG. 3 and 4.
Such an ATM switch may be implemented as taught by U.S. Referring now to FIG. 3, in the subject invention, a
Pat. No. 5,455,825. which is incorporated by reference primary queue 70 is used for queuing cells to destinations
herein. The ATM switch 10 has incoming lines 14. which are corresponding to unblocked and active virtual channels. The
coupled to input processing modules 16, the outputs of primary queue 70 is implemented similar to the queue and
which are respectively applied to a queue and search module 15 search module 18 as shown in FIG. 1 and as described in
18 and a cell buffer memory 20. The queue and search U.S. Pat. No. 5,455,825. In addition to this primary queue
module 18 is under control of a control unit 22, which, 70. the subject invention uses a queuing decision module 72
among other things, controls input processing modules 16, which determines whether an incoming cell should be
as well as output processing modules 24. Each input pro- placed in a primary queue 70 or in a secondary queue 74.
cessing module 16 and output processing module 24 20 The queuing decision module uses a virtual channel table 76
includes a microprocessor and memory or other means by to determine whether a virtual channel corresponding to the
which it can be configured or reconfigured by control unit 22 incoming cell is blocked or unblocked. Cells for blocked
to perform any process appropriate to the requirements of channels are directed to the secondary queue 74. Cells for
the network for each cell arriving at or leaving the switch. unblocked channels are directed to the primary queue 70.
The outputs of queue and search module 18 are applied to 25 The secondary queue 74 may be implemented in a manner
respective output processing modules 24, as are the outputs similar to a priority queue described in, for example, "An
of cell buffer memory 20. As illustrated at 26, the output of Efficient Self-Timed Queue Architecture for ATM Switch
input processing module 16 contains destination LSI's," by H. Kondoh et at., in Custom Integrated Circuit
information, tags and buffer addresses, which are coupled to Conference, San Diego, May 1994 (Kondoh et al. 1994) and
queue and search module 18. Additionally, as illustrated at "A New ATM Switch Architecture Based on STS-type
28, cell headers and bodies are coupled to cell buffer Shared Buffering and its LSI Implementation," by K.
memory 20. Oshima, et al., in Proceedings of International Switching
In operation, a ceU arrives at an input processing module Symposium 1992., Yokohama, Japan, October 1992, pp.
16 via an input link 14. Input processing module 16 per- 35 359-363, which are hereby incorporated by reference. These
forms cell-by-cell processing on the arriving cell. In addition references describe a queue of cells for which a destination
to the normal housekeeping functions required in every vector is provided. The queue is searched for the ceU closest
ATM switch, input processing module 16 computes a tag to 11,(5 head of *e <lueue which matches a selected destina
value for each cell according to the scheduling algorithm for tlon
the virtual channel of the cell. The tag value is also based on ^ In this invention, cells are copied from the secondary
the state of that channel and arrival time of the cell. A Virtual queue 74 to the primary queue 70 by the requeuing module
channel is an end-to-end connection of a particular stream of 78. This requeuing module 78 accesses the virtual channel
data, separate from all other streams of data. In an ATM table to determine the virtual channel for which a cell from
network, a virtual channel is identified by a field of bits in the secondary queue 74 should be selected. Generally
the header of the cell. Input processing module 16 also 45 speaking, the requeuing module 78 accesses a cell from the
computes and updates the status information of the virtual secondary queue 74 when the virtual channel becomes
channel and other information maintained by the switch. unblocked. For example, it may replace a transmitted cell
Following the calculation, the tag, the destination infor- from me primary queue with another cell from the secondary
mation and the buffer address of the cell are coupled to 1ueue for a virtual channel of the same priority class as the
queue and search module 18, where they are stored in the 50 virtual channel of the transmitted cell,
queue. The cell header and cell data are coupled to cell The secondary queue 74 is not an identical implementa
buffer memory 20. At this point, the address, destination and tion of the priority queue of Kondoh et al. Rather, the
tag of the cell are now in the queue, and its cell header and destination bits described by Kondoh et al. are replaced by
data are stored in the cell buffer memory. Input processing virtual channel information. The search performed by
module 16 is then free to accept and begin processing the 55 requeuing module 78 on secondary queue 74 is for the first
next cell. Therefore, the input processing must be completed cell of a given virtual channel.
within the time allotted to one cell cycle of the correspond- FIG. 3 also shows, a destination selection module 80
ing input link 14. that is the time required to receive an ATM which indicates the destination to which a cell should be
cell at the bandwidth of the input link. transmitted from the primary queue 70. This indicated
Under control of control unit 22, the queue and search 60 destination is also used by requeuing module 78 to select the
module searches the queue in turn for a cell with destination next virtual channel for which a cell is to be copied from the
bits corresponding to each output processing module 24. secondary queue to the primary queue.
Output processing module 24 performs any remaining cal- This ATM switch can support broad class of admission
culations required before the cell can be transmitted. It then control and scheduling algorithms for real-time
transmits the cell over output link 30 to another node in the 65 communication, including weighted fair queuing, earliest
network or to its ultimate destination. The searching accom- deadline first rate monotonic, virtual clock, and many
plished by the queue and search module 18 must be com- others. It also can support credit-based flow control for