ATM local area network switch with dual queues

1 2

ATM LOCAL AREA NETWORK SWITCH from incoming to outgoing network links. Traffic is handled

WITH DUAL QUEUES in HFC- order according to the ATM rules, but a small

number of priority levels, usually two, are provided to FIELD OF THE INVENTION support applications with real-time communication require

This invention relates to digital communication networks 5 ments in a very limited way. Unfortunately, a handful of in which cells or packets traverse a network from node to statically assigned priorities is barely adequate for even node, and more particularly to a digital communication moderate-sized local area networks with a lot of advanced, network switch having an improved system for scheduling rapidly evolving applications. Furthermore, when applicable order that cells are transmitted from one node to another tions need t0 transmit continuous media, such as audio and node in the network. 10 video, 01 when they need predictable response in real time,

it is virtually impossible to make any kind of predictions or BACKGROUND OF THE INVENTION guarantees about the quality and timeliness of network

In general, in a digital communication network, messages service, or streams of information are subdivided into sequences of An advanced ATM network switch is described in U.S. small units called packets or cells. Such cells or packets are 15 Pat No- 5,455,825. This ATM network switch includes a transmitted from node to node. In each node a switch, called <lueue and buffer memory which is shared for all output lines a network switch, selects both the order of transmitting such of me switch. That is, input cells from all input ports are cells or packets and the next node to which they are to be deposited directly into the common buffer memory. The transmitted. Thus, in such networks the digital information common queuing and shared buffers improve statistical reaches its ultimate destination in a timely manner. It is 20 multiplexing, and provides both faster performance and desirable that these network switches be capable of support- lower c°st A reference to each cell in the shared buffer is ing network traffic of various characteristics including traffic placed in a shared queue. For each input cell, a numerical tag requiring hard real-time guarantees of timely delivery, con- is determined and included in the queue. Cells are selected tinuous media traffic for audio and video, and traffic requir- 110111 the <lueue for transmission based on these tags using a ing very rapid response. 25 queue and search module. Multiple classes of traffic includ

One important kind of digital communications network is in8 traffic are supported in the switch, and each

called an Asynchronous Transfer Mode (ATM) network. class can have its ownscheduhng algorithm and pohcy, such ATM networks provide for the transmission of data from one as simple-priority, FIFO or real-time. While such a switch point or node in the network to one or more other points or ,n has advantages, it is difficult to control blocking of nodes by the subdivision of the data or information into 30 transmission on a virtual channel with this switch. Thus it sequences of small cells of fixed size which are then mav^^J^tH^9 'round-robm 01 credit-based transmitted through the network from node to node. Such nodes include ATM switches which provide fast packet or cell switching and routing between nodes of the network. 35 General principles of ATM networks are described in articles The subject invention uses two queues to control flow for by J. Bryan Lyles and Daniel C. Swinehart, "The Emerging blocked and unblocked channels. In one embodiment, the Gigabit Environment and the Role of Local ATM," IEEE system has a tag-based primary queue which contains ATM Communications Magazine, vol. 30, #4, April 1992, pp. cells organized by priority and a secondary queue which 52-58, and by C. Lamb, "Speeding to the ATM," Unix m contains ATM cells which are not yet scheduled for Review, vol. 10, #10, October 1992, pp. 29-36. transmission, e.g., due to a channel being blocked, and

One of the major problems with ATM networks is the which is organized by virtual channel. A queuing decision problem of scheduling of cells to be transmitted by each module is provided to determine in which queue an incomswitch. The cells are in general buffered at each switch in ing ATM cell should be deposited. A requeueing module queues. Assuming no congestion, these cells are received 45 operates when an event occurs that unblocks a particular from an incoming link at a switch and immediately trans- virtual channel. The requeuing module, on occurrence of mitted over an outgoing link to another destination. such an event, accesses the secondary queue to obtain However, when cells arrive over multiple input links and another cell, to assign it priority and to move it to the must be transmitted onto the same output link at the same primary queue. The queuing decision module, along with a time, it is necessary to form a queue of cells so that they can 50 virtual channel table, can be used easily to block virtual be transmitted in the desired order. channels when necessary. The combination of queues also

In order to accommodate the scheduling of which cells are allows for round robin scheduling, to be transmitted at what time and in what order, it is

common to utilize a first-in, first-out (FIFO) ordering system BRIEF DESCRIPTION OF THE DRAWING

in which cells are transmitted according to their order of 55 These and other features of the subject invention will be arrival at the switch. Li the case of networks which support better understood m view 0f the following Detailed Descripreal time applications, cells are also typically assigned tion taken ^ conjunction with the Drawing of which: priorities and stored in separate queues by priority. ... „ ^. , . ,

Subsequently, cells are transmitted in an order dictated by TM*.lls » "°ck ^fT bating a logical architecture the priorities of the separate queues. It will be appreciated 60 of ... ATM switch showing a queue and searchmodule

. , . r , . ,. , under control of a control unit;

that these simple systems can only support a limited number

and class of real time applications, because the FIFO and m®- 2 TM a block diagram of a switch in accordance with priority scheduling mechanisms can only provide limited the invention;

guarantees of timely transmission without loss of data. FIG. 3 is a block diagram showing the dual queue

For instance, first generation switches for ATM local and 65 architecture of the present invention; wide area networks provide very simple scheduling algo- FIG. 4 is a more detailed block diagram of FIG. 3 with rithms for scheduling and dispatching communication traffic more details of the two queues; and

kinds of flow control.

SUMMARY OF THE INVENTION

3 4

FIG. 5 is a block diagram of the secondary queue, pleted for all output processing units within the time allotted

registers in a FIFO for representing each cell in the queue, to one cell cycle of the fastest associated input link 14 and

a search circuit for selecting cells from the queue which output link 30 of the switch. U.S. Pat. No. 5,455.825

match a particular virtual channel, and a bus read circuit for describes the queue and search system in more detail,

reading out information from the queue; 5 Referring now to FIG. 2. the subject invention uses a dual

FIG. 6 is a schematic diagram of four queue entries input queue architecture 18A in connection with a controller 22A.

to the search circuit in FIG. 5; The remaining structure of the switch 10A is generally the

same as switch 10 as shown in FIG. 1. More details of the

DETAILED DESCRIPTION dual queue architecture 18A and the controller 22A will now

Referring now to FIG. 1, an ATM Switch 10 is provided. 10 be described hi connection with FIG. 3 and 4.

Such an ATM switch may be implemented as taught by U.S. Referring now to FIG. 3, in the subject invention, a

Pat. No. 5,455,825. which is incorporated by reference primary queue 70 is used for queuing cells to destinations

herein. The ATM switch 10 has incoming lines 14. which are corresponding to unblocked and active virtual channels. The

coupled to input processing modules 16, the outputs of primary queue 70 is implemented similar to the queue and

which are respectively applied to a queue and search module 15 search module 18 as shown in FIG. 1 and as described in

18 and a cell buffer memory 20. The queue and search U.S. Pat. No. 5,455,825. In addition to this primary queue

module 18 is under control of a control unit 22, which, 70. the subject invention uses a queuing decision module 72

among other things, controls input processing modules 16, which determines whether an incoming cell should be

as well as output processing modules 24. Each input pro- placed in a primary queue 70 or in a secondary queue 74.

cessing module 16 and output processing module 24 20 The queuing decision module uses a virtual channel table 76

includes a microprocessor and memory or other means by to determine whether a virtual channel corresponding to the

which it can be configured or reconfigured by control unit 22 incoming cell is blocked or unblocked. Cells for blocked

to perform any process appropriate to the requirements of channels are directed to the secondary queue 74. Cells for

the network for each cell arriving at or leaving the switch. unblocked channels are directed to the primary queue 70.

The outputs of queue and search module 18 are applied to 25 The secondary queue 74 may be implemented in a manner

respective output processing modules 24, as are the outputs similar to a priority queue described in, for example, "An

of cell buffer memory 20. As illustrated at 26, the output of Efficient Self-Timed Queue Architecture for ATM Switch

input processing module 16 contains destination LSI's," by H. Kondoh et at., in Custom Integrated Circuit

information, tags and buffer addresses, which are coupled to Conference, San Diego, May 1994 (Kondoh et al. 1994) and

queue and search module 18. Additionally, as illustrated at "A New ATM Switch Architecture Based on STS-type

28, cell headers and bodies are coupled to cell buffer Shared Buffering and its LSI Implementation," by K.

memory 20. Oshima, et al., in Proceedings of International Switching

In operation, a ceU arrives at an input processing module Symposium 1992., Yokohama, Japan, October 1992, pp.

16 via an input link 14. Input processing module 16 per- 35 359-363, which are hereby incorporated by reference. These

forms cell-by-cell processing on the arriving cell. In addition references describe a queue of cells for which a destination

to the normal housekeeping functions required in every vector is provided. The queue is searched for the ceU closest

ATM switch, input processing module 16 computes a tag to 11,(5 head of *e <lueue which matches a selected destina

value for each cell according to the scheduling algorithm for tlon

the virtual channel of the cell. The tag value is also based on ^ In this invention, cells are copied from the secondary

the state of that channel and arrival time of the cell. A Virtual queue 74 to the primary queue 70 by the requeuing module

channel is an end-to-end connection of a particular stream of 78. This requeuing module 78 accesses the virtual channel

data, separate from all other streams of data. In an ATM table to determine the virtual channel for which a cell from

network, a virtual channel is identified by a field of bits in the secondary queue 74 should be selected. Generally

the header of the cell. Input processing module 16 also 45 speaking, the requeuing module 78 accesses a cell from the

computes and updates the status information of the virtual secondary queue 74 when the virtual channel becomes

channel and other information maintained by the switch. unblocked. For example, it may replace a transmitted cell

Following the calculation, the tag, the destination infor- from me primary queue with another cell from the secondary

mation and the buffer address of the cell are coupled to 1ueue for a virtual channel of the same priority class as the

queue and search module 18, where they are stored in the 50 virtual channel of the transmitted cell,

queue. The cell header and cell data are coupled to cell The secondary queue 74 is not an identical implementa

buffer memory 20. At this point, the address, destination and tion of the priority queue of Kondoh et al. Rather, the

tag of the cell are now in the queue, and its cell header and destination bits described by Kondoh et al. are replaced by

data are stored in the cell buffer memory. Input processing virtual channel information. The search performed by

module 16 is then free to accept and begin processing the 55 requeuing module 78 on secondary queue 74 is for the first

next cell. Therefore, the input processing must be completed cell of a given virtual channel.

within the time allotted to one cell cycle of the correspond- FIG. 3 also shows, a destination selection module 80

ing input link 14. that is the time required to receive an ATM which indicates the destination to which a cell should be

cell at the bandwidth of the input link. transmitted from the primary queue 70. This indicated

Under control of control unit 22, the queue and search 60 destination is also used by requeuing module 78 to select the

module searches the queue in turn for a cell with destination next virtual channel for which a cell is to be copied from the

bits corresponding to each output processing module 24. secondary queue to the primary queue.

Output processing module 24 performs any remaining cal- This ATM switch can support broad class of admission

culations required before the cell can be transmitted. It then control and scheduling algorithms for real-time

transmits the cell over output link 30 to another node in the 65 communication, including weighted fair queuing, earliest

network or to its ultimate destination. The searching accom- deadline first rate monotonic, virtual clock, and many

plished by the queue and search module 18 must be com- others. It also can support credit-based flow control for