« PrécédentContinuer »
O I 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
000 0 00 101 0 0 0 0 00 I 0 I I III
IMAGE SIGNAL DECODING SYSTEM FOR DECODING MODIFIED HUFFMAN CODES AT HIGH SPEEDS
BACKGROUND OF THE INVENTION
The present invention relates to an image signal decoding system and, more particularly, to an image signal decoding system capable of decoding modified Huffman codes at a high speed.
Heretofore, run-length codes have been employed as image-compressing codes for use with high-speed facsimile machines. As a run-length coding scheme, the Comite Consultatif Internationale Telegraphique et 15 Telegraph (CCITT) recommends a modified Huffman coding scheme. The modified Huffman coding scheme is a coding scheme for code-compressing image signals such as a code that has encoded an arbitrary run-length number by combining 54 kinds of make-up codes which 20 encodes up to 1728 pixels by every 64 pixels with 128 kinds of terminating codes in which every 64 pixels from pixel 0 to pixel 63 by one pixel, so as to allow the run-length number to correspond white run-length number and black run-length number to white pixels 25 and black pixels, respectively.
Such a system for decoding image signals encoded by the modified Huffman coding scheme of this type is known, for example, by an image signal decoding system as disclosed in Japanese Patent Publication 3Q (Kokoku) No. 16,071/1989. The image signal decoding system as disclosed in this prior patent publication is arranged to perform the decoding of white or black run-length information of facsimile data encoded by the modified Huffman coding scheme by a small fixed mem- 35 ory capacity. In this system, the kind and run length of codes are prepared so as to correspond to each of the modified Huffman codes (hereinafter referred to as "MH codes"), and the MH codes are decoded by providing data of 10 bits obtained by processing the re- 40 ceived MH codes as a ROM (read only memory) access address, reading the data in the ROM and developing it into dots.
However, the image signal decoding system in the prior art technology presents the problem that no atten- 45 tion is paid to the processing speed for decoding, so that the demand for processing image signals at a high speed is not met.
SUMMARY OF THE INVENTION 5Q
Therefore, the present invention has the object to provide an image signal decoding system for performing the decoding of the MH codes at a high speed.
In order to achieve the aforesaid object, the present invention consists of an image signal decoding system 55 adapted to decode an image data of a variable length whose data is compressed by MH code, comprising a decode-encode circuit for decoding input of a modified Huffman code with its end portion equalized, encoding a code length, a code kind and a run length by decoded 60 content and generating them; and a rotator for shifting a bit data; wherein decoding object data is cut by a fixed length of 13 bits, the cut data is inputted into and decoded by the decode-encode circuit through the rotator, the data is shifted by a bit number of a code length 65 as the output result of decoding so as to equalize an end portion of the decoding object data which comes next with an input end portion of an encode-decode circuit,
and a decoding object data cut next is continuously input into the decode-encode circuit and decoded.
From the top of the MH code data as the decoding object data, 13 bits of the maximum code length of the MH code are cut, and the 13 bits are supplied to the decode-encode circuit as an input data for decoding after their end portions are equalized by the rotator. At the concurrent time, a color-designating data indicative of the white run length or the black run length is supplied to the decode-encode circuit. The decode-encode circuit decodes and determines the code by its decoder and decodes for forming each data of the code length, the code kind and the run length of the MH code by its encoder. And, for decoding the next code, the cut data is shifted by the rotator by the bit number of the code length as the decoding output result to thereby equalize the end portion of the next decoding object data with the input end portion of the encode-decode circuit. Further, the rest is supplied to the decode-encode circuit, followed by the next cut decoding object data, for decoding the next MH code.
As described hereinabove, the image signals of the decoding object data whose data is compressed by the MH code of a variable length are decoded in order.
In this case, the input data is shifted by the rotator and input in such a manner that the end portion of the input data is caused to agree with the input end portion of the decode-encode circuit. The data supplied to the rotator is temporarily stored in the buffer register having a plurality of data regions, and an empty data region supplied to the rotator from the buffer register is supplemented with a next decoding object data from the read register.
In order to perform the data transfer among the rotator, the buffer register and the read register, there are provided a first transfer processing means for transferring data from the buffer register to a data storage region in which decoded data of the rotator is stored and a second transfer processing means for transferring data from the read register to a region for transmitted data of the buffer register. These means allow the data transfer between the registers. The processing by the first and second transfer processing means can be performed concurrently with and parallel to each other, thereby shortening the period of time for decoding the MH code data.
As described hereinabove, the decode-encode circuit is designed to perform a logic operation of a hard logic, unlike the processing by making access to a memory such as reading ROM data, etc., so that the decoding processing can be performed at a high speed.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a block diagram showing the circuit configuration of an essential portion of an image signal decoding processor for decoding an image signal according to an embodiment of the present invention.
FIGS, 2a, 2b, 3a and 3b are diagrams showing the control over transferring data among the data buffer, the read register, the buffer register and the rotator.
FIGS. 4, 5 and 6 are diagrams showing a flow of data for decoding codes from the buffer register to the codelength register, the code kind register and the runlength register.
DESCRIPTION OF THE PREFERRED
FIG. 1 is a block diagram showing the circuit configuration of an essential portion of an image signal decod- 5 ing processor for decoding image signals according to an embodiment of the present invention. In FIG. 1, reference numeral 1 stands for a data buffer, reference numeral 2 for a read register, reference numeral 3 for a buffer register, reference numeral 4 for a rotator, refer- 10 ence numeral 5 for a decode-encode circuit, reference numeral 6 for a code-length register, reference numeral 7 for a code-kind register, reference numeral 8 for a run-length register, reference numeral 9 for a rotatingnumber register, reference numeral 10 for an adder, 15 reference numeral 11 for an address register for the data buffer 1, and reference numeral 12 for a color-signal designating register.
The block diagram of FIG. 1 indicates the circuit configuration for decoding MH (modified Huffman) 20 code data. All of the MH code data to be decoded is stored in the data buffer The address register 11 stores an address for designating read data of the data buffer 1. The data read out from the data buffer 1 is stored in the read register 2 and then transmitted to and temporarily 25 stored in the data buffer register 3. The data transmitted to the buffer register 3 is further transmitted to the rotator 4 which shifts the bits of the data by the bit number in accordance with the code length, thereby equalizing the end portion of the input data and supply- 30 ing it into the decode-encode circuit 5. The decodeencode circuit 5 decodes the codes of the input data and encodes each of them in accordance with the decoded contents, thereby generating each data of the code length, the code kind and the run length of the results 35 obtained by decoding the MH codes. Each of the data of the code length, code kind and run length is stored in the code-length register 6, the code-kind register 7, and the run-length register 8, respectively.
The code-length data obtained by decoding and 40 stored in the code-length register 6 is generated to the adder 10 to which the data from the rotating-number register 9 is added and which adds the contents of the rotating-number register 9 to the code-length data of the code-length register 6, thereby using the resulting 45 data as a rotating number for the code to be decoded next. The resulting data is stored again in the rotatingnumber register 9. On the other hand, the data of the rotating-number register 9 is supplied to the rotator 4 to thereby shift the data of the buffer register 3, thereby 50 determining a shift quantity upon inputting into the decode-encode circuit 5. The color-designating data of a white run length or a black run length, stored in the color-designating register 12 is supplied to the decodeencode circuit 5 and the color designation of the code to 55 be decoded is shifted to each other, thereby allowing the decode-encode circuit 5 to decode the white runlength number or the black run-length number.
Description will specifically be made of the processing for decoding the MH codes by using the image 60 signal decoding processor having the aforesaid structure.
First, as initial setting, all of the MH codes to be decoded are stored in the data buffer 1. Each of the address register 11, the read register 2, the buffer regis- 65 ter 3, the rotating-number register 9 and the color-signal designating register 12 is set to "0". The "0" designated by the color-signal designating register 12 means that
the MH code as a decoding object is initially a white run length. On the other hand, the color-signal designating register 12 is initially set to "1" in order to allow the decoding processing to start with a black run length.
In starting the decoding processing, first, the address register 11 reads MH code data of 4 bytes from the data buffer 1 and sets it in the read register 2. In this case, no MH code data is set in the buffer register 3, so that the contents of the read register 2 are transmitted to the buffer register 3. Then, +4 is added to the contents of the address register 11 and 4 bytes of the MH code data are read again from the data buffer 1 to thereby set it to the read register 2. Thereafter, the MH code data stored in the buffer register 3 is transmitted to the rotator 4 which in turn rotates the MH code data to the left on the basis of the value of the rotating-number register 9. As a result, the MH code as the decoding object is set to the left end, thereby inputting 13 bits (the maximum code length of the MH code) from the left end of the MH code data stored temporarily in the rotator 4 into the decode-encode circuit 5.
The decode-encode circuit 5 selects an active decoder of the decode circuit on the basis of 13 bits of the input MH code data and the color signal of the colorsignal designating register 12 designating the white run length or the black run length, thereby decoding the MH code data. Further, the code length, code kind and run length of the decoded MH code are generated by the encode circuit on the basis of the contents of the output of the decoder and output to the code-length register 6, the code-kind register 7, and the run-length register 8, respectively. A decision is then made on the basis of the contents of the code kind of the MH code output from the decode-encode circuit 5 to determine if the decoded MH code is a terminating code or a makeup code. If the decoded MH code is the terminating code, on the one hand, the color signal of the color-signal designating register 12 is inverted for decoding a code coming next. If the decoded MH code is the makeup code, on the other hand, the color signal is left as it is.
Then, in order to update the value of the rotatingnumber register 9, the values of of the code-length register 6 and the rotating-number register 9 are input into the adder 10, and the addition is performed by the adder 10 on the basis of the input data supplied to the adder 10. The addition results are stored again in the rotatingnumber register 9.
When the next code is to be decoded, like when the previous code has been decoded, the MH code data set to the buffer register 3 is transmitted to the rotator 4 and the MH code data within the rotator 4 is rotated to the left only by the rotating number stored in the rotatingnumber register 9, thereby inputting 13 bits from the left end of the rotated results and the color signal of the color-signal designating register 12 in the decodeencode circuit 5. As a consequence, the code length, the code kind and the run length of the currently decoded MH code are generated and stored again in the codelength register 6, the code-kind register 7 and the runlength register 8, respectively. Further, the contents of the rotating-number register 9 are updated by the contents of the code-length register 6, and the color signal data of the color-signal designating register 9 is set again by the contents of the code-kind register 7. The decoding processing of the MH code which follows is performed in the same manner as described hereinabove.