Fully connected multiple FCU-based architectures reduce requirements for Tag SRAM size and memory read latencies. A preferred embodiment of a symmetric multiprocessor system includes a switched fabric (switch matrix) for data transfers that provides multiple concurrent buses that enable greatly increased...http://www.google.fr/patents/US6633945?utm_source=gb-gplus-shareBrevet US6633945 - Fully connected cache coherent multiprocessing systems
Fully connected cache coherent multiprocessing systems
