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LOOP MANIPULATION IN A BEHAVIORAL
CROSS-REFERENCE TO RELATED
This application claims the benefit of Gutberlet et al., U.S. Provisional Application No. 60/575,210, entitled "DEPENDENT LOOP MERGING IN A BEHAVIORAL SYNTHESIS TOOL," filed May 28,2004, which is incorporated herein 10 by reference.
This application relates generally to behavioral synthesis 15 tools for creating integrated circuits (e.g., field programmable gate arrays) and, more particularly, relates to the analysis and processing of loops within a design.
With the advent of electronic design automation (EDA), the design of complex hardware systems no longer begins with a hardware circuit diagram. Instead, circuit design typically begins with a software program that describes the 25 behavior or functionality of the hardware system. In one exemplary approach, the behavior or functionality of an electronic circuit design may be described using a hardwaredescription language (HDL) (e.g., VHDL, Verilog, or other such language). Circuit designers direct behavioral synthesis 30 tools to generate alternate architectures by modifying constraints (e.g., clock period, number and type of data path elements, and desired number of clock cycles). Behavioral synthesis tools convert the HDL program into a register transfer level (RTL) description. The RTL description is used to 35 ultimately generate a netlist that includes a list of components in the circuit and the interconnections between the components. This netlist is used to create the physical integrated circuit.
An example of HDL source code, shown in Table 1 below, 40 declares three variables (a, b, and c) that are arrays. Each array contains 1024 8-bit words. The code first declares a "subtype" to define the type of each element in the array. The code then defines a "type" to represent the array itself. Finally, the variables are declared, each variable representing an array. 45
SUBTYPE word IS unsigned (7 DOWNTO 0);
TYPE array_type IS ARRAY (integer RANGE <> ) of word;
VARIABLE a, b, c: array_type (0 to 1023); 50
Generally, the variables can be accessed using loops, such as the loop shown below in Table 2. When an array is mapped to memory, each element in the array is mapped to a memory location. For example, a(0) maps to address 0, a(l) maps to 55 address 1, and a(1023) maps to address 1023.
FOR i IN 0 TO 15 LOOP 60
a(i) = b(i)«c(i) + 4; END LOOP;
After the designer completes the HDL source code, the designer may run the source code through the synthesis tool. 65 A typical synthesis tool generates a report that the designer can use to analyze the performance of the circuit. For
example, the user can examine the area and latency of the circuit to determine whether the current loop configuration is acceptable. If the loop configuration is not acceptable, the designer typically returns to an editor, re-edits the source code to unroll or pipeline loops, and runs the source code through the synthesis tool again. Such a technique for modifying the design is time consuming and inefficient. Moreover, the designer cannot easily visualize how the loop configuration changes the design while modifying the source code.
RTL methodologies have previously sufficed to simulate and design simple hardware blocks but today fall far short in many ways. Design complexity of new digital signal processing (DSP) applications has outpaced traditional RTL methods. As such, designers have moved to C++ or Matlab® to quickly validate their algorithms. While this higher abstraction has helped system verification, it has also widened the technology gap between the system designers using highlevel languages and the hardware designers who hand-code the RTL.
Designs have evolved from single- or multi-block functional units into large systems that include embedded cores and complex hardware implementing proprietary computeintensive algorithms. Despites these advances, engineers still use iterative RTL methods that involve manual steps such as micro-architecture definition, handwritten RTL, and area/ speed optimization through RTL synthesis. This process is slow and error-prone. Moreover, since both the micro-architecture and destination technology characteristics are hardcoded into the RTL description, the whole notion of RTL reuse or retargeting becomes impractical for real applications.
Complete or enhanced control over how a design is synthesized to hardware is needed and would provide several advantages. For example, an architectural constraints tool presenting a graphical view of all ports, arrays, and loops in a design could allow for any of various high-level constraints to be applied. For example, these constraints could include loop unrolling, pipelining, and merging. Such tools could provide precise control of a hardware implementation, allowing for interactive convergence on significantly better quality designs in much less time.
Various new and non-obvious exemplary methods for loop unrolling, pipelining, and merging are disclosed together with related apparatus. The methods can be used, for example, to implement a design for an Application Specific Integrated Circuit (ASIC) or field programmable gate array (FPGA) or other such programmable logic device.
One of the disclosed embodiments is an exemplary method for designing a hardware circuit in a behavioral synthesis tool. This method involves finding loops and merging some or all of them together. According to this method, a first loop is detected. The first loop contains items (e.g., statements that access variables). A second loop is also detected, the second loop also containing items (e.g., statements that access variables). In some embodiments, a variable in the second loop is dependent upon a variable in the first loop. In other embodiments, several variables in either the second loop or the first loop might be dependent upon other variables in either of the two loops. According to this method, the two loops are partially or fully merged with each other. In other embodiments, the loops are merged with other loops.
Another of the disclosed embodiments is an exemplary method for designing integrated circuits (e.g., FPGAs). According to this method, a source code representation of a
hardware circuit is analyzed and loops within the representation are identified. In one embodiment, a first loop is dependent on a second loop. In other embodiments, any number of loops may be dependent upon other loops. At least two loops are then merged together. 5
Another disclosed embodiment is an exemplary method within a user interface for a behavioral synthesis tool. According to this method, a number of choices for setting a mergeable directive is provided to the user (e.g., designer). One of the choices is selected, thereby setting the mergeable 10 directive. In one embodiment, a TRUE mergeable directive provides for merging of loops that can be merged together. In another embodiment, a default choice may be provided based on a heuristic (e.g., TRUE).
Any of the disclosed embodiments may be performed by a 15 computer programmed with computer-executable instructions stored on a computer-readable medium. In these embodiments, the computer-executable instructions cause the computer to perform any of the disclosed embodiments. Moreover, any of the disclosed embodiments can be used to 20 update or modify circuit design information stored on a computer-readable medium. Accordingly, modified design databases storing circuit designs retimed by the methods described herein are also disclosed. Such methods can be performed, for instance, on a stand-alone workstation or via a 25 network.
These and other features are set forth below with reference to the accompanying figures.
BRIEF DESCRIPTION OF THE FIGURES 30
FIG. 1 is a block diagram showing an exemplary system for generating an integrated circuit.
FIG. 2 is a flowchart showing an exemplary method for generating an integrated circuit according to a hardware 35 design tool, such as the system shown in FIG. 1.
FIG. 3 is a flowchart showing a more detailed exemplary method for generating an integrated circuit.
FIG. 4 is a system diagram of a client/server network as may be used in performing the disclosed methods. 40
FIG. 5 is a flowchart showing the creation of a database using, for example, the network of FIG. 4.
Disclosed below are representative embodiments of methods for analyzing and processing loops within a circuit design. The disclosed methods should not be construed as limiting in any way. Instead, the present disclosure is directed toward novel and non-obvious features and aspects of the 50 various disclosed embodiments, alone and in various combinations and sub-combinations with one another. The methods are not limited to any specific aspect or feature or combinations thereof, nor do the disclosed methods require that any one or more specific advantages be present or problems be 55 solved.
Although the operations of some of the disclosed methods are described in a particular, sequential order for convenient presentation, it should be understood that this manner of description encompasses rearrangement, unless a particular 60 ordering is required by specific language set forth below. For example, operations described sequentially may in some cases be rearranged or performed concurrently. Moreover, for the sake of simplicity, the attached figures may not show the various ways in which the disclosed methods can be used in 65 conjunction with other methods. Additionally, the description sometimes uses terms like "determine" and "evaluate" to
describe the disclosed methods. These terms are high-level abstractions of the actual operations that are performed. The actual operations that correspond to these terms will vary depending on the particular implementation and are readily discernible by one of ordinary skill in the art.
The disclosed embodiments can be applied to a wide variety of sequential integrated circuits. A sequential integrated circuit (or sequential circuit) is one whose outputs depend not only on its current inputs, but also on the past sequence of inputs, possibly arbitrarily far back in time. Examples of sequential circuits include programmable logic devices (PLDs) such as field programmable gate arrays (FPGAs), application-specific integrated circuits (ASICs), and systems-on-a-chip (SoCs). A sequential circuit contains at least one sequential circuit element, such as a flip-flop, synchronous RAM element, or latch. A sequential circuit element (or sequential element) generally refers to any circuit element whose outputs state changes occur at times specified by a free-running clock signal.
Any of the disclosed methods can be performed using software stored on a computer-readable medium and executed on a computer. Such software can comprise, for example, an electronic-design-automation (EDA) software tool used, for instance, for logical or physical synthesis. Such software can be executed on a single computer or on a networked computer (e.g., via the Internet, a wide-area network, a local-area network, a client-server network, or other such network). For clarity, only certain selected aspects of the software-based implementations are described. Other details that are well known in the art are omitted. For example, it should be understood that the disclosed technology is not limited to any specific computer language, program, or computer. For the same reason, computer hardware is not described in detail.
Integrated Circuit Generation
FIG. 1 shows a system 100 for generating an integrated circuit. A designer typically creates a behavioral description of an integrated circuit by generating source code file 102 using a separate editor (not shown). The source code is described generically as HDL and may be written in C, C++, VHDL, Verilog, or any other suitable language. The source code might also be written in a C++ derivative language such as SystemC. Once the source code 102 is complete, a behavioral synthesis tool 104 reads in the source code file 102 and allows a designer to evaluate and modify the circuit architecture early in the design process. In particular, the source code 102 may be read into an intermediate database 106 that holds the behavioral description as a data structure. This data structure, called a synthesis intermediate format (SIF), is modifiable by the user such as through use of a graphical user interface (GUI) 108. The behavior synthesis tool can identify loops within the source code. In one embodiment, a GUI also allows the designer to unroll and or pipeline identified loops where execution time is greatest. By processing loops (e.g., merging, pipelining, etc.), the circuit design can be optimized. Additionally, the designer may also quickly evaluate the area and latency associated with different pipelining, unrolling, and merging combinations. Once the designer is satisfied with the architecture, the RTL code is generated as shown at 120. Further processing is then performed on the RTL code to ultimately generate the integrated circuit. The behavioral synthesis tool 104 may be executed on any desired general purpose computer having any display device or monitor for displaying the GUI and having any desired user input, such as a mouse, keyboard, or any other input device.