ADD ADDR_REGB VLAN_TAG_SZEC;
XOR TCP_CSUML11 MINUSJI, WSRAM2_XPOSE;
/*
* SET FRAME LEN INTO TEMPLATE HEADER FOR MAC SEQR.
* FRAMELEN = TEMPLATE HDR LEN - 2
*/
MOVEL ADDR_REGA STCB_TEMPLATE+TPL_TMPLTLEN; /* POINT TO TEMPLATE LENGTH */
MOVE CRO SRAM2, LIT_TO_ADDR_REGB STCB_XMTBYTCNT;
COMP CRO MIN_FRAME_LEN, JCT LT '$ + 3';
/* MAKE SURE FRAME IS MIN LENGTH */
SUBL NULL CRO XMT_HDDR_SIZE_SRAM, WSRAM4; /* TEMPLATE HDR - 2 7
JMP '$ + 2';
MOVEL SRAM4 ETHER_MIN_TU; /* MIN ETHER FRAME LEN = 60 (+CRC) */
ADD CRO SIZEOF_XMITHDR+7C; I* PREPARE TO ROUNDUP XFER SIZE 7
MOVE RAM_BASE PDDSCPTR, LIT_TO_ADDR_REGB DMA_CMD_WD;
ANDNL SRAM4+ CRO H'3';
/* PDES->IXFR_SZ ROUNDED TO 8-BYTE BNDRY 7
MOVE SRAM4+ LNBPL8; /* PDES->DST_ADDR = 7
ADDL SRAM4 TCBSRAML5 STCB_XMIT_BUFFER; /* PDES->SRC_ADDR = 7
/* XXXDMA ORL CH_CMD CTXT_RPROC CCR_S2D; 7
/* SET UP TO DMA THE ACK FROM SRAM TO DRAM 7
MOVE Q_CTRL Q_S2DC; /* SELECT S2D DMA 7
MOVE Q_DATA PDDSCPTR;
JCF Q_OP_DONE'$-1';
MOVE CTXT_RTNADL14 PC, JMP PROC_SUSPEND; /* SUSPEND 7
MOVE RAM_BASE TCBSRAML5; /* RESUME 7