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STATIC BRANCH PREDICTION
MECHANISM FOR CONDITIONAL BRANCH
INSTRUCTIONS
CROSS-RERERENCE TO RELATED 5
APPLICATIONS
This application is a divisional application of U.S. patent application Ser. No. 09/272,225, filed Mar. 18, 1999 and entitled "STATIC BRANCH PREDICTION MECHANISM FOR CONDITIONAL BRANCH INSTRUCTIONS"; and is related to the following: U.S. Pat. No. 6,189,091, entitled, APPARATUS AND METHOD FOR SPECULATIVELY UPDATING GLOBAL BRANCH HISTORY AND RESTORING SAME UPON BRANCH MISPREDICTION DETECTION; Ser. No. 09/203,900, entitled, METHOD AND APPARATUS FOR PERFORMING BRANCH PREDICTION USING BRANCH TEST TYPE; and Ser. No. 09/203,884, entitled, METHOD AND APPARATUS FOR PERFORMING BRANCH PREDICTION COMBINING STATIC AND DYNAMIC BRANCH PREDICTORS; all of the aforementioned applications having the same assignee and having common inventors.
FIELD OF THE INVENTION
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This invention relates in general to the field of instruction execution in computers, and more particularly to an apparatus and method for predicting the outcome of branch instructions in a pipeline microprocessor.
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BACKGROUND OF THE INVENTION
An application program for execution on a microprocessor consists of a structured series of macro instructions that are stored in sequential locations in memory. A current 3J instruction pointer within the microprocessor points to the address of the instruction currently being executed and a next instruction pointer within the microprocessor points to the address of the next instruction for execution. During each clock cycle, the length of the current instruction is 4Q added to the contents of the current instruction pointer to form a pointer to a next sequential instruction in memory. The pointer to the next sequential instruction is provided to logic that updates the next instruction pointer. If the logic determines that the next sequential instruction is indeed 4J required for execution, then the next instruction pointer is updated with the pointer to the next sequential instruction in memory. Thus, macro instructions are fetched from memory in sequence for execution by the microprocessor.
Obviously, because a microprocessor is designed to 50 execute instructions from memory in the sequence that they are stored, it follows that a program configured to execute macro instructions sequentially from memory is one which will run efficiently on the microprocessor. For this reason, most application programs are designed to minimize the 55 number of instances where macro instructions are executed out of sequence. These out-of-sequence instances are known as jumps, or branches.
A program branch presents a problem because most conventional microprocessors do not simply execute one 60 instruction at a time. Rather, a present day microprocessor consists of a number of pipeline stages, each stage performing a specific function. Instructions, inputs, and results from one stage to the next are passed in synchronization with a pipeline clock. Hence, several instructions may be executing 65 in different stages of the microprocessor pipeline within the same clock cycle. As a result, when logic within a given
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stage determines that a program branch is to occur, then previous stages of the pipeline, that is, stages that are executing instructions following in sequence, must be cast out to begin execution of sequential macro instructions beginning with the instruction directed by the branch, or the branch target instruction. This casting out of previous pipeline stages is known as flushing and refilling the pipeline.
A conditional branch is a branch that may or may not occur, depending upon an evaluation of some specified condition. And, this evaluation is typically performed in later stages of the microprocessor pipeline. To preclude wasting many clock cycles associated with flushing and refilling the pipeline, present day microprocessors also provide logic in an early pipeline stage that predicts whether a conditional branch will occur or not. If it is predicted that a conditional branch will occur, then only those instructions prior to the early pipeline stage must be flushed, including those in the instruction buffer. Even so, this is a drastic improvement; correctly predicted branches are executed in roughly two clock cycles. But an incorrect prediction takes many more cycles to execute than if no branch prediction mechanism had been provided in the first place. The accuracy of branch predictions in a pipeline processor therefore significantly impacts the processor's performance, for better or worse.
Yet, present day branch prediction techniques chiefly predict the outcome of a given conditional branch instruction in an application program based upon outcomes obtained when the conditional branch instruction was previously executed within the same instance of the application program. Historical branch prediction, or dynamic branch prediction, is effective because conditional branch instructions tend to exhibit repetitive outcome patterns when executed within an application program.
The historical outcome data is stored in a branch history table that is accessed using the address of a conditional branch instruction—a unique identifier for the instruction. A corresponding entry in the branch history table contains the historical outcome data associated with the conditional branch instruction. A dynamic prediction of the outcome of the conditional branch instruction is made based upon the contents of the corresponding entry in the branch history table.
Yet, because most present day microprocessors have address ranges on the order of gigabytes, it is not practical for a branch history table to be as large as the microprocessor's address range. Because of this, smaller branch history tables are provided, on the order of kilobytes, and only low order bits of a conditional branch instruction's address are used as an index into the table. But this presents another problem: because low order address bits are used to index the branch history table, two or more conditional branch instructions can index the same entry. This is known as aliasing. As such, the outcome of a more recently executed conditional branch instruction will replace the outcome of a formerly executed conditional branch instruction that is aliased to the same table entry. If the former conditional branch instruction is encountered again, its historical outcome information is unavailable to be used for a dynamic prediction.
Because dynamic predictions are sometimes not available, an alternative prediction is made for the outcome of a conditional branch instruction, usually based solely upon some static attribute of the instruction, such as the relative direction of a branch target instruction as compared to the address of the conditional branch instruction. This
