|A peak detector circuit that responds rapidly to power transients, and yet is able |
to avoid interpreting data fluctuations as power transients by generating dual
peak signals from an amplifier's differential output signal, where the dual peak
signals have data ripple ...
|An electronic amplifier circuit that provides improved gain control linearity |
characteristics resulting from having a controllable field effect transistor (FET)
acting as a degeneration resistance (degeneration resistance FET) and a
controllable load resistance FET. The overall gain function of the amplifier ...
|A variable gain amplifier and offset cancellation loop circuit and methods for |
tracking and correcting DC offset errors that may vary in accordance with the gain
of the variable gain amplifier.
|An example method includes receiving a phase correction signal representing a |
phase difference between a source signal and a reference signal, generating a
first control voltage from the phase correction signal using a charge pump circuit,
generating a second control voltage from the phase correction ...
|An initial phase-loading circuit (IPLC) for a fractionally-spaced linear equalizer (|
FSLE) includes a signal coupling component adapted to be coupled to the FSLE
in a configuration so as to selectively introduce time-shifted discrete signals. The
FSLE includes a set of initial filter tap coefficients that provide a ...
|Briefly, in accordance with one embodiment of the invention, an adaptive |
equalizer comprises: a digital filter including filter tap coefficients; a slicer; and a
filter tap coefficient update block. The filter, slicer and coefficient update block are
configured so as to perform at least one burst update of the filter tap ...
|A pipelined adaptive infinite impulse response (PAIIR) filter is disclosed including |
an adaptive section and a non-adaptive section, where the PAIIR filter is
responsive to first and second input signals. The PAIIR filter includes a plurality of
delays and a first polynomial signal generator. The plurality of delays ...
|A high-speed optical transmitter comprises multiple digital lanes that are |
provided to a bank of digital-to-analog converters. The analog signals are then
used to Phase Shift Keyed (PSK) modulation using a Chirp Managed Laser (CML
)-based transmitter, and potentially using dual polarization.