WO2008102651A1 - Film isolant amorphe et transistor en couches minces - Google Patents

Film isolant amorphe et transistor en couches minces Download PDF

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Publication number
WO2008102651A1
WO2008102651A1 PCT/JP2008/052091 JP2008052091W WO2008102651A1 WO 2008102651 A1 WO2008102651 A1 WO 2008102651A1 JP 2008052091 W JP2008052091 W JP 2008052091W WO 2008102651 A1 WO2008102651 A1 WO 2008102651A1
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WO
WIPO (PCT)
Prior art keywords
film
insulator film
amorphous
amorphous insulator
ratio
Prior art date
Application number
PCT/JP2008/052091
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English (en)
Inventor
Hisato Yabuta
Nobuyuki Kaji
Ryo Hayashi
Original Assignee
Canon Kabushiki Kaisha
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority to US12/522,371 priority Critical patent/US8044402B2/en
Application filed by Canon Kabushiki Kaisha filed Critical Canon Kabushiki Kaisha
Priority to CN200880005092.5A priority patent/CN101611474B/zh
Priority to EP08710970.8A priority patent/EP2126966B1/fr
Publication of WO2008102651A1 publication Critical patent/WO2008102651A1/fr

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/51—Insulating materials associated therewith
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28158—Making the insulator
    • H01L21/28167—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation
    • H01L21/28194—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation by deposition, e.g. evaporation, ALD, CVD, sputtering, laser deposition
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/4908—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET for thin film semiconductor, e.g. gate of TFT
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H01L29/78609—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device for preventing leakage current
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate

Definitions

  • the present invention relates to an amorphous insulator film and a thin-film transistor using the same .
  • liquid crystal displays, plasma displays, and organic EL displays have been actively developed regardless of sizes thereof.
  • TFT thin-film transistor
  • a TFT using an amorphous oxide semiconductor film for a channel can be applied to a flexible display using a plastic substrate formed at room temperature. Therefore, active research and development have been made as disclosed in Applied Physics Letters, Volume 89, 112123-1, pp.l to 3.
  • an amorphous InGaZnO 4 thin film is used which is deposited as an amorphous oxide semiconductor channel layer by a sputtering method.
  • a Y 2 O 3 film is used which is deposited as a gate-insulator film by a sputtering method.
  • the Y2O3 film serving as the gate-insulator film is more expensive than a silicon oxide (SiO 2 ) film normally used as the gate-insulator film of the TFT. Therefore, the conversion of the Y 2 O 3 film to a silicon-containing amorphous insulator film such as a Si ⁇ 2 film has been expected.
  • the silicon-containing amorphous insulator film such as the SiO 2 film is normally produced by a chemical vapor deposition method (CVD method) in many cases.
  • CVD method chemical vapor deposition method
  • a deposition temperature equal to or higher than 300 0 C is normally necessary, so it is difficult to form the insulator film on a plastic substrate.
  • the amorphous oxide semiconductor film used for the TFT can be formed by a sputtering method at a deposition temperature equal to or lower than 300 0 C. Therefore, it is desirable that the insulator film can be formed by a sputtering method as in the case where the amorphous oxide semiconductor film is formed. This is because a substrate having a low heat resistance, such as the plastic substrate, can be employed.
  • the conventional silicon-containing amorphous insulator film deposited by a sputtering method is inferior in insulation characteristic to the conventional silicon-containing amorphous insulator film deposited by a CVD method. Therefore, the silicon-containing amorphous insulator film deposited by the sputtering method has not been put to practical use up to now.
  • the silicon-containing amorphous insulator film deposited by the sputtering method has not been put to practical use up to now.
  • Japanese Patent Application Laid-Open No. H02-90568 it is desired to improve the performance of the insulator film formed by the sputtering method.
  • an SiO 2 film containing 5 atomic% or less of Ar is disclosed as a magnetic gap material of a magnetic head.
  • no applications of the Si ⁇ 2 film to the gate-insulator film of the TFT are disclosed.
  • An object of the present invention is to provide an amorphous insulator film which is made of Si oxide and has an excellent characteristic, and a thin-film transistor using the amorphous insulator film.
  • the inventors of the present invention have extensively studied an amorphous insulator film which is formed by a sputtering method and made of silicon oxide. As a result, findings about a correlation between the Ar content of the insulator film and an insulation characteristic thereof have been obtained, and an amorphous insulator film which has an excellent insulation characteristic and is made of silicon oxide has been invented.
  • the present invention has been accomplished on the basis of the findings described above, and is directed to an amorphous insulator film which is used as a gate-insulator film of a thin-film transistor and which comprises silicon (Si) oxide, wherein the amorphous insulator film includes Ar and an amount of Ar included therein is equal to or larger than 3 atomic percent in terms of atomic ratio with respect to Si.
  • the amorphous insulator film excellent in insulation characteristic can be obtained. Further, when the insulator film according to the present invention is used, a thin-film transistor whose performance is superior to, and whose cost is lower than, conventional thin film transistors can be obtained by a low-temperature manufacturing process .
  • FIG. 1 is a graph illustrating a correlation between an Ar/Si ratio of an amorphous insulator film according to the present invention and a current density thereof at the time of application of 1 MV/cm.
  • FIG. 2 is a schematic view illustrating a structure of a parallel-plate capacitor device for I-V characteristic evaluation which is used in Experimental Example and Example 1 according to the present invention.
  • FIG. 3 is a schematic view illustrating a structure of a bottom gate TFT which is used in Experimental Example and Example 2 according to the present invention.
  • FIG. 4 is a graph illustrating a transfer characteristic of a bottom gate TFT whose gate- insulator film is the amorphous insulator film according to the present invention and whose channel layer is an amorphous oxide film.
  • the film formation condition of the silicon oxide film is not necessarily sufficiently described in the above prior art documents and thus the details of the film formation condition are unclear. Also, a correlation between the amount of Ar contained in the formed silicon oxide film and the insulation characteristic of the silicon oxide film is not disclosed.
  • the inventors of the present invention focused on and extensively studied a relationship between the amount of Ar contained in the silicon oxide film and the insulation characteristic of the silicon oxide film.
  • Silicon oxide films were produced by a sputtering method in various conditions, and accordingly, it was found that there is a correlation between the amount of Ar contained in the silicon oxide film and the insulation characteristic thereof.
  • the silicon oxide film excellent in insulation characteristic can be obtained by setting the amount of Ar contained in the silicon oxide film to a suitable range, thus the present invention has been completed.
  • a silicon oxide amorphous insulator film which is made of silicon oxide and contains Ar where the amount of Ar contained in the amorphous insulator film is within a specific range in atomic ratio with respect to Si. Therefore, an insulating film having excellent characteristics can be obtained. When the insulating film is used, a device having an excellent characteristic, such as a thin-film transistor, can be obtained.
  • the amorphous insulator film according to the present invention is the Si oxide amorphous insulator film.
  • the amorphous insulator film contains Ar, and the amount of Ar contained in the amorphous insulator film is equal to or larger than 3 atomic percent in terms of atomic ratio with respect to Si (Ar/Si ⁇ 3 at.%) (hereinafter, atomic percent is referred to as "at.%")
  • the atomic ratio is desirably equal to or larger than 4 atomic% (Ar/Si ⁇ 4 at.%) and more desirably equal to or larger than 5 atomic% (Ar/Si ⁇ 5 at.%).
  • the upper limit of the amount of Ar contained in the amorphous insulator film is desirably equal to or smaller than 17 atomic% (Ar/Si ⁇ 17 at.%) and more desirably equal to or smaller than 16 atomic% (Ar/Si ⁇ 16 at.%) .
  • the amorphous insulator film made of silicon oxide contains the above-mentioned amount of Ar and has an excellent insulation characteristic.
  • an amorphous insulator film made of silicon oxide can be obtained in which a current density when an electric field of 1 MV/cm is applied to the amorphous insulator film is equal to or smaller than l ⁇ l ⁇ ⁇ 6 A/cm 2 .
  • an amorphous insulator film made of silicon oxide can be obtained in which a current density when an electric field of 1 MV/cm is applied to the amorphous insulator film is equal to or smaller than 3 ⁇ lO 7 A/cm 2 .
  • a sputtering method is desirably used as the method of forming the amorphous insulator film according to the present invention.
  • An rf magnetron sputtering method is more desirably used as the sputtering method.
  • the amorphous insulator film according to the present invention is desirably formed at a temperature equal to or lower than 300 0 C and more desirably formed at room temperature.
  • the amorphous insulator film is desirably formed in a state in which at least one of the potential of the substrate and the potential of the substrate holder at the time of film formation is positive relative to the ground potential or in an open state in which at least one of the substrate and the substrate holder is spaced from the ground.
  • An example of a device using the amorphous insulator film according to the present invention includes a TFT.
  • the amorphous insulator film is used as a gate-insulator film thereof.
  • the channel layer is desirably formed by a sputtering method.
  • the channel layer is desirably formed by a vacuum deposition method including a pulsed laser deposition (PLD) method.
  • PLD pulsed laser deposition
  • the amorphous insulator film whose insulation characteristic is excellent is obtained.
  • a TFT which is higher in performance and lower in cost as compared with a conventional TFT can be manufactured at temperature lower than conventional manufacturing process temperature .
  • a device which has high performance, stability and reliability can be provided at low cost. Even in a situation where temperature cannot be raised during a manufacturing process, such as a case where the above devise is formed on a plastic substrate, the device can be formed at low temperature.
  • the inventors of the present invention have studied the amorphous insulator film made of silicon oxide which is formed by a sputtering method, and particularly, examined a correlation between the amount of Ar contained in the amorphous insulator film and the insulation characteristic thereof.
  • a parallel-plate rf magnetron sputtering apparatus was used as a sputtering apparatus
  • An SiO 2 plate with a diameter of 75 mm was used as a target.
  • the substrate temperature at the time of film formation was set at room temperature.
  • a glass substrate on which a Ti/Au/Ti multilayer was formed as an electrode was used as a substrate.
  • the amorphous insulator film made of silicon oxide was produced in an open state (also referred to as "floating state") in which the substrate and a substrate holder are spaced from the ground.
  • Film formation parameters which were varied were a substrate position (substrate was provided in the direction vertical to the target or in the obliquely upper direction to the target), a deposition pressure (0.06 Pa to 2 Pa) , a film formation gas composition
  • the amount of Ar contained in the produced amorphous insulator film made of silicon oxide was measured by fluorescent X-ray analysis.
  • the Ar/Si ratio in the amorphous insulator film was controlled by reducing the film formation gas composition (Ar/0 2 ratio) as the film formation parameter. For example, a ratio of O 2 in the film formation gas was increased to increase the Ar/Si ratio. Even in a film formation condition in which O 2 is not introduced and thus only
  • FIG. 1 illustrates the dependence of a current density on the Ar/Si ratio at the time of application of 1 MV/cm, which was obtained from the result of the measured current-voltage characteristics of the amorphous insulator film.
  • a leak current characteristic in which the current density at the time of application of 1 MV/cm was equal to or smaller than l ⁇ l ⁇ ⁇ 6 A/cm 2 was obtained in a region of Ar/Si ⁇ 3 at . % .
  • the amorphous insulator film having such a leak current characteristic was applied to a gate-insulator film of a TFT having a structure illustrated in FIG. 3.
  • an off- current value of a transfer characteristic of the TFT as illustrated in FIG. 4 was equal to or smaller than 10 ⁇ 12 A, thus the excellent TFT characteristic was exhibited.
  • the region of Ar/Si ⁇ 3 at . % can be used as an index for the amorphous insulator film (made of Si oxide) exhibiting the excellent insulation characteristic.
  • the leak current value is reduced with an increase in the amount of Ar.
  • the leak current value is held to be substantially constant regardless of the amount of Ar increases.
  • an effect of reduction in leak current along with an increase in the amount of Ar becomes maximum in the region in which the Ar/Si ratio is equal to or larger than 4 at.%.
  • the region of Ar/Si ⁇ 5 at.% can be defined as a region in which the effect of reduction in leak current along with the increase in the amount of Ar is obtained in a high probability.
  • sputtering power was set to be 5OW, 2OW, and 1OW to produce amorphous insulator films made of Si oxide.
  • the Ar/Si ratios of the obtained amorphous insulator films had the following relationship: Ar/Si (film produced at 50 W) > Ar/Si (film produced at 10 W) > Ar/Si (film produced at 20 W)
  • the sputtering power was equal to or larger than 20 W, the Ar/Si ratio increased along with reduction in sputtering power.
  • the Ar/Si ratio at the sputtering power of 10 W is smaller than the Ar/Si ratio at the sputtering power of 20 W, and it is considered that an Ar/Si ratio of 0.162 of the film produced at 20 W is a maximum value of the Ar/Si ratio of the film. Even in the film whose Ar/Si ratio was 0.162 (film produced at 20 W), the insulation characteristic was excellent. Therefore, according to the present invention, the upper limit value of the Ar/Si ratio is considered to be 17 at .
  • the region can be defined as a region in which the effect of reduction in leak current is obtained in a higher probability.
  • the Si oxide film After the film formation, if only the Si oxide film is taken out from a vacuum chamber to be exposed to the air, water molecules penetrate the Si oxide film and stay in the micro pores. It is considered that the water molecules in the Si oxide film cause the insulation characteristic thereof to deteriorate (contribute electrical conduction thereof) .
  • the insulator film according to the present invention is formed in the vacuum chamber, Ar is introduced into the micro pores, with the result that water molecules are prevented from entering the insulator film.
  • the density of the insulator film of this experimental example was measured by an X-ray reflectivity (XRR) measurement method. As a result, the density increases as the amount of Ar (Ar/Si ratio) increases. This means that there is no change or a small change in volume of the insulator film which is caused by the introduction of Ar into the film.
  • the insulator film having the excellent insulation characteristic can be obtained in the region of the Ar/Si ratio as described above.
  • Si-O bonds may be broken by Ar ion impact as known in the prior art, to thereby form an insulator film whose insulation characteristic is inferior.
  • the film formation condition is important.
  • a current density when an electric field of 1 MV/cm is applied is equal to or smaller than IxIO "5 A/cm 2 , desirably equal to or smaller than 3 ⁇ lO "7 A/cm 2 .
  • the insulator film according to the present invention is different from the film produced in the conventional film formation condition (such as high-energy Ar ion hit condition) and corresponds to the film having the Ar/Si ratio and the insulation characteristic (current density) as described above.
  • the conventional film formation condition such as high-energy Ar ion hit condition
  • Example 1 Amorphous Insulator Film
  • Example 1 of the present invention a multilayer of a Ti layer (5 nm in thickness), an Au layer (40 nm in thickness), and a Ti layer (5 nm in thickness) was formed as a bottom electrode on a glass substrate by a sputtering method using a Ti target and an Au target.
  • An SiU2 film was formed on the multilayer with a thickness of 100 nm by an rf magnetron sputtering apparatus using an SiC> 2 target.
  • the film formation condition is as follows. The substrate was placed at such a position that the center of the substrate was located in a direction tilted by approximately 55 degrees relative to the vertical direction of the center of the target and a distance between the center of the target and the center of the substrate was approximately 130 mm.
  • the substrate and the substrate holder were maintained in an electrical insulation state (open state) .
  • the film formation gas was only an Ar gas.
  • a film formation gas pressure was 0.1 Pa.
  • Sputtering power was 20 W.
  • a temperature set at the time of film formation and an indication temperature of a thermometer each were 20 0 C.
  • an Si substrate for Ar/Si composition analysis using a fluorescent X-ray was placed. The film formation was performed on both the substrates at the same time.
  • reference numeral 1 denotes the glass substrate
  • reference numeral 2 denotes the bottom electrode (Ti/Au/Ti)
  • reference numeral 3 denotes the SiO 2 film
  • reference numeral 4 denotes top electrode ( ⁇ .3 mm, Ti/Au/Ti).
  • the SiO 2 film formed on the Si substrate for Ar/Si ratio evaluation was subjected to X-ray fluorescence (XRF) analysis analysis to evaluate the amount of Ar and the amount of 0 which were contained in the SiO 2 film. Then, a ratio of the number of Ar atoms to the number of Si atoms (Ar/Si ratio) in the film was obtained on the basis of an Si value and an 0 value which were obtained by XRF analysis of an SiO 2 film formed on a carbon substrate .
  • XRF X-ray fluorescence
  • FIG.l illustrates a correlation between the Ar/Si ratio of the formed SiO 2 film and a current density when an electric field of 1 MV/cm was applied.
  • a point plotted at the rightmost position of FIG. 1 corresponds to the value of the SiO 2 film obtained in this example.
  • the current density when the electric field of 1 MV/cm was applied was equal to or smaller than l ⁇ l ⁇ ⁇ 6 A/cm 2 and equal to or smaller than 3*10 ⁇ 7 A/cm 2 .
  • Example 2 TFT Device
  • a Ti (5 nm)/Au(40 ran) /Ti (5 nm) multilayer was formed as a gate electrode 12 on a glass substrate 11 by electron beam evaporation and shaped by a photolithography method and a lift-off method.
  • SiO 2 film having a thickness of 100 nm was formed as a gate insulator film (referred to also as
  • SiO 2 film 13 on the gate electrode 12 by means of an rf magnetron sputtering apparatus using an SiO 2 target.
  • the film formation condition is as follows. Sputtering power was 400 W. A sputtering gas pressure was 0.1 Pa. A sputtering gas composition Ar/O 2 was 50/50. The film formation was performed at room temperature. The amount of Ar contained in the Si ⁇ 2 film in such a condition was 4.9% in terms of the Ar/Si ratio. After that, the Si ⁇ 2 film 13 was shaped by a photolithography method and an etching method.
  • an In x Ga y Zn z O v film having a thickness of 40 nm was formed as a channel layer 14 at room temperature by rf magnetron sputtering using an InGaOs(ZnO) target.
  • the obtained In x Ga y Zn z 0 v film was amorphous.
  • Symbols x, y, z, and v are 0 ⁇ x ⁇ l, 0 ⁇ y ⁇ l, 0 ⁇ z ⁇ l, and 0 ⁇ v ⁇ 4, respectively.
  • the In x Ga y Zn z 0 v film 14 was processed to a necessary size by etching and then a source electrode 15 and a drain electrode 16 were formed by a photolithography method and a lift-off method.
  • the electrode material film is an Au (150 nm)/Ti(5 nm) multilayer and a film formation method thereof is an electron beam vapor deposition method.
  • TFT devices were manufactured through the above-mentioned process. Among the obtained TFT devices, a transfer characteristic (drain current-gate voltage characteristic) of a TFT device having a gate length of 10 ⁇ m and a gate width of 60 ⁇ m was measured, and such a characteristic as illustrated in FIG. 4 was obtained. As illustrated in FIG. 4, the TFT device was obtained in which a gate leak current value was small even in the case of application of a high voltage, exhibiting an excellent characteristic.
  • the amorphous oxide semiconductor channel TFT device having the excellent characteristic can be obtained at room temperature. This is effective not only in a process at room-temperature process but also in a process at raised temperature. In particular, this is effective in a process at temperatures less than 300 0 C to which a CVD process cannot be applied. Even in the case of a TFT device using a crystalline oxide semiconductor as a TFT channel, the same effect is obtained.

Abstract

L'invention concerne un film isolant amorphe constitué de silicone (Si). Ce film isolant amorphe comprend de l'Ar, la quantité d'Ar comprise dans ce film étant supérieure ou égale à 3% en atomes en termes de rapport atomique par rapport à Si.
PCT/JP2008/052091 2007-02-19 2008-02-04 Film isolant amorphe et transistor en couches minces WO2008102651A1 (fr)

Priority Applications (3)

Application Number Priority Date Filing Date Title
US12/522,371 US8044402B2 (en) 2007-02-19 2008-02-02 Amorphous insulator film and thin-film transistor
CN200880005092.5A CN101611474B (zh) 2007-02-19 2008-02-04 非晶绝缘体膜和薄膜晶体管
EP08710970.8A EP2126966B1 (fr) 2007-02-19 2008-02-04 Transistor en couches minces avec film isolant amorphe

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2007-037994 2007-02-19
JP2007037994A JP5354862B2 (ja) 2007-02-19 2007-02-19 アモルファス絶縁体膜及び薄膜トランジスタ

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WO2008102651A1 true WO2008102651A1 (fr) 2008-08-28

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US (1) US8044402B2 (fr)
EP (1) EP2126966B1 (fr)
JP (1) JP5354862B2 (fr)
CN (1) CN101611474B (fr)
TW (1) TWI377605B (fr)
WO (1) WO2008102651A1 (fr)

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US8604469B2 (en) * 2008-06-05 2013-12-10 Samsung Display Co., Ltd. Thin film transistor array panel
JP2015122518A (ja) * 2009-10-09 2015-07-02 株式会社半導体エネルギー研究所 シフトレジスタ

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JP5213422B2 (ja) * 2007-12-04 2013-06-19 キヤノン株式会社 絶縁層を有する酸化物半導体素子およびそれを用いた表示装置
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JP2012033836A (ja) 2010-08-03 2012-02-16 Canon Inc トップゲート型薄膜トランジスタ及びこれを備えた表示装置
JP2012119474A (ja) * 2010-11-30 2012-06-21 Teijin Ltd 薄膜トランジスタ、及びその製造方法
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CN101611474B (zh) 2014-12-03
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